W9412G6JH-5 Winbond Electronics, W9412G6JH-5 Datasheet - Page 4

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W9412G6JH-5

Manufacturer Part Number
W9412G6JH-5
Description
IC DDR-400 SDRAM 128MB 66TSSOPII
Manufacturer
Winbond Electronics
Datasheet

Specifications of W9412G6JH-5

Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
128M (8Mx16)
Speed
200MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOPII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W9412G6JH-5
Manufacturer:
MURATA
Quantity:
640 000
Part Number:
W9412G6JH-5
Manufacturer:
WINBOND/华邦
Quantity:
20 000
1. GENERAL DESCRIPTION
W9412G6JH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM); organized as 2M words × 4 banks × 16 bits. W9412G6JH delivers a data bandwidth of up to
500M words per second (-4). To fully comply with the personal computer industrial standard,
W9412G6JH is sorted into two speed grades: -4 and -5. The -4 is compliant to the DDR500/CL3 and
CL4 specification. The -5 is compliant to the DDR400/CL3 specification.
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9412G6JH is ideal for main memory in
high performance applications.
2. FEATURES
2.5V ±0.2V Power Supply for DDR400
2.4V~2.7V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6µS Refresh interval (4K/64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
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Publication Release Date: Apr. 02, 2010
W9412G6JH
Revision A01

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