CY7C1393BV18-167BZC Cypress Semiconductor Corp, CY7C1393BV18-167BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1393BV18-167BZC
• Description: IC SRAM 18MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1393BV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
Application Example
Figure 1
Document #: 38-05623 Rev. *D
MASTER
ASIC)
BUS
(CPU
or
shows four DDR-II SIO used in an application.
SRAM 1 Input CQ#
SRAM 4 Input CQ#
SRAM 1 Input CQ
SRAM 4 Input CQ
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
DATA IN
Address
BWS#
R/W#
LD#
Vt
R
R
R = 50Ohms
D
A
LD
LD
#
#
R/W
R/W
Vt = V
#
#
SRAM 1
W
B
S
W
#
B
#
REF
Figure 1. Application Example
C C#
K
CQ#
CQ
ZQ
K#
Q
R = 250Ohms
to lock it to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR-I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII™/DDRII.
CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18
D
A
R
Vt
Vt
LD
#
R/W
SRAM 4
#
W
B
S
#
C C# K
CQ#
CQ
ZQ
K#
Q
R = 250Ohms
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