CY7C1315JV18-300BZXC Cypress Semiconductor Corp, CY7C1315JV18-300BZXC Datasheet - Page 20

• Manufacturer Part Number: CY7C1315JV18-300BZXC
• Description: IC SRAM SYNC 18KB QDR2 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315JV18-300BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Up Sequence in QDR II SRAM
Power up and initialize QDR II SRAMs in a predefined manner
to prevent undefined operations.
Power Up Sequence
■
■
Document Number: 001-12562 Rev. *D
Apply power and drive DOFF either HIGH or LOW (All other
inputs are HIGH or LOW).
❐
❐
❐
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
Apply V
Apply V
Drive DOFF HIGH.
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
.
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
Figure 3. Power Up Waveforms
/
V
REF
DDQ
.
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input has low
phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Fix High (or tie to V DDQ )
> 1024 Stable clock
Stable)
CY7C1313JV18/CY7C1315JV18
CY7C1311JV18/CY7C1911JV18
KC Var
.
Start Normal
Operation
Page 20 of 27
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