CY7C1315JV18-300BZXC Cypress Semiconductor Corp, CY7C1315JV18-300BZXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1315JV18-300BZXC
• Description: IC SRAM SYNC 18KB QDR2 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315JV18-300BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-12562 Rev. *D
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
23. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
24. This part has a voltage regulator internally; t
25. These parameters are extrapolated from the input timing parameters (t
26. t
27. At any voltage and temperature t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
operated and outputs data with the output timings of that frequency range.
initiated.
included in the t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
KHKH
). These parameters are only guaranteed by design and are not tested in production
V
K Clock and C Clock Cycle Time
Input Clock (K/K; C/C) HIGH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.49
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to Clock (K, K) Rise (RPS, WPS)
Double Data Rate Control Setup to Clock (K, K) Rise
(BWS
D
Address Hold after Clock (K/K) Rise
Control Hold after Clock (K /K) Rise (RPS, WPS)
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS
D
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
Clock (C and C) Rise to High-Z (Active to High-Z)
Clock (C and C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
DD
[X:0]
[X:0]
[22, 23]
CHZ
(Typical) to the First Access
Hold after Clock (K/K) Rise
0
Setup to Clock (K/K) Rise
0
, BWS
, BWS
is less than t
POWER
1
1
, BWS
, BWS
CLZ
is the time that the power must be supplied above V
and t
2
2
, BWS
, BWS
CHZ
less than t
3
3
)
)
[25]
Description
AC Test Loads and
[26, 27]
[24]
KHKH
CO
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
.
Waveforms. Transition is measured ± 100 mV from steady-state voltage.
[26, 27]
CY7C1313JV18/CY7C1315JV18
CY7C1311JV18/CY7C1911JV18
DD
[25]
minimum initially before a read or write operation can be
–0.45
–0.45
–0.27
–0.45
1024
1.32
1.32
1.24
1.24
Min Max Min Max
3.3
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
300 MHz
30
1
0
–
–
–
–
1.45
0.45
0.45
0.27
0.45
0.20
8.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–0.45
–0.45
–0.30
–0.45
1024
0.35
0.35
0.35
0.35
1.55
1.55
4.0
1.6
1.6
1.8
0.5
0.5
0.5
0.5
250 MHz
30
1
0
–
–
–
–
KC Var
Page 23 of 27
0.45
0.45
0.30
0.45
0.20
8.4
1.8
) ia already
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Cycles
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback