MT47H32M8BP-37E:B TR Micron Technology Inc, MT47H32M8BP-37E:B TR Datasheet - Page 15

• Manufacturer Part Number: MT47H32M8BP-37E:B TR
• Description: IC DDR2 SDRAM 256MBIT 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M8BP-37E:B TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 256M (32M x 8)
• Speed: 3.75ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 500ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 160mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1049-2

Table 3: FBGA 60-Ball – x4, x8 and 84-Ball – x16 Descriptions
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
LDM, UDM, DM
DQ[15:0] (x16)
RAS#, CAS#,
DQ[3:0] (x4)
DQ[7:0] (x8)
DQS, DQS#
BA0, BA1
Symbol
CK, CK#
A[12:0]
WE#
ODT
CKE
CS#
Type
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command deter-
mines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[1:0]) or
all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE
command.
Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[1:0] define which mode register, including MR,
EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and negative edge of CK#.
Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is depend-
ent on the DDR2 SDRAM configuration and operating mode. Taking CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-
down (row active in any bank). CKE is synchronous for power-down entry, power-down exit,
output disable, and self refresh entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (exclud-
ing CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level once V
during the power-on and initialization sequence, it must be maintained for proper opera-
tion of the CKE receiver. For proper SELF-REFRESH operation, V
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered high. CS# provides for external
bank selection on systems with multiple ranks. CS# is considered part of the command code.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to match
that of DQ and DQS balls. LDM is DM for the lower byte DQ[7:0], and UDM is DM for the
upper byte DQ[15:8].
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termina-
tion resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of
the following balls for the x4 configuration: DQ[3:0], DQS, DQS#, and DM; for the x8 config-
uration: DQ[7:0], DQS, DQS#, RDQS, RDQS#, and DM; and for the x16 configuration:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if
disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
tered.
Data input/output: Bidirectional data bus for the 16 Meg x 16 configuration.
Bidirectional data bus for the 64 Meg x 4 configuration.
Bidirectional data bus for the 32 Meg x 8 configuration.
Data strobe: DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
DD
is applied during first power-up. After V
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
256Mb: x4, x8, x16 DDR2 SDRAM
REF
©2003 Micron Technology, Inc. All rights reserved.
must be maintained.
REF
has become stable