C8051F313R Silicon Labs, C8051F313R Datasheet - Page 109
Manufacturer Part Number
8-bit Microcontrollers - MCU 8KB 10ADC
Specifications of C8051F313R
8-bit Microcontrollers - MCU
Data Bus Width
Maximum Clock Frequency
Program Memory Size
Data Ram Size
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
A/d Bit Size
A/d Channels Available
Data Rom Size
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
Number Of Timers
Program Memory Type
Factory Pack Quantity
Supply Voltage - Max
Supply Voltage - Min
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized may cause a system reset. See register VDM0CN (Figure 9.1)
0: Read: Last reset was not a power-on or V
1: Read: Last reset was a power-on or V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
read-modify-write instructions read and modify the source enable only. This applies to bits:
C0RSEF, SWRSF, MCDRSF, PORSF.
monitor is a reset source.
SFR Definition 9.2. RSTSRC: Reset Source
monitor reset; all other reset flags indeterminate.
monitor reset. Write: V
monitor is enabled
monitor is not a