AT45DB021D-SH-T Atmel, AT45DB021D-SH-T Datasheet - Page 2

• Manufacturer Part Number: AT45DB021D-SH-T
• Description: IC FLASH 2MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB021D-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (1024 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.
2
The device is optimized for use in many commercial and industrial applications where high-density, low-pin count,
low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the Atmel
programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read
operations. The AT45DB021D is enabled through the chip select pin (CS) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
Pin Configurations and Pinouts
Table 1-1.
Symbol
CS
SCK
SI
SO
WP
RESET
V
GND
Atmel AT45DB021D
CC
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be
deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output
pin (SO) will be in a high-impedance state. When the device is deselected, data will not be accepted on
the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is
required to end an operation. When ending an internally self-timed operation such as a program or erase
cycle, the device will not enter the standby mode until the completion of the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to
and from the device. Command, address, and input data present on the SI pin is always latched on the
rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including
command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked
out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection
Register will be protected against program and erase operations regardless of whether the Enable Sector
Protection command has been issued or not. The WP pin functions independently of the software
controlled protection method. After the WP pin goes low, the content of the Sector Protection Register
cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device will
simply ignore the command and perform no operation. The device will return to the idle state once the CS
pin has been deasserted. The Enable Sector Protection command and Sector Lockdown command,
however, will be recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be
used. However, it is recommended that the WP pin also be externally connected to V
possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the
internal state machine to an idle state. The device will remain in the reset condition as long as a low level
is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a
high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin
during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin
be driven high externally.
Device Power Supply: The V
Operations at invalid V
Ground: The ground reference for the power supply. GND should be connected to the system ground.
Pin Configurations
CC
voltages may produce spurious results and should not be attempted.
CC
pin is used to supply the source voltage to the device.
®
AT45DB021D does not require high input voltages for
CC
whenever
Asserte
d State
3638J–DFLASH–5/10
Low
Low
Low
–
–
–
–
–
Output
Power
Groun
Type
Input
Input
Input
Input
Input
d