UPMU-M3L1xLCD-B-EK Silicon Labs, UPMU-M3L1xLCD-B-EK Datasheet
UPMU-M3L1xLCD-B-EK
Specifications of UPMU-M3L1xLCD-B-EK
Related parts for UPMU-M3L1xLCD-B-EK
UPMU-M3L1xLCD-B-EK Summary of contents
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ARM Cortex-M3 CPU - 50 MHz maximum frequency - Single-cycle multiplication, hardware division support - Nested vectored interrupt control (NVIC) with 8 priority levels Memory - 32–256 kB flash, in-system programmable - 8–32 kB SRAM with configurable low power ...
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Rev 0.5 ...
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Related Documents and Conventions ...............................................................................5 1.1. Related Documents........................................................................................................5 1.1.1. SiM3L1xx Reference Manual.................................................................................5 1.1.2. Hardware Access Layer (HAL) API Description ....................................................5 1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5 1.2. ...
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SiM3L1xx 4.7.2. UART (UART0).................................................................................................... 47 4.7.3. SPI (SPI0, SPI1) .................................................................................................. 48 4.7.4. I2C (I2C0) ............................................................................................................ 48 4.8. Analog .......................................................................................................................... 49 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)................................................... 49 4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) ......................................................... 49 4.8.3. Low Current Comparators (CMP0, CMP1) .......................................................... ...
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Related Documents and Conventions 1.1. Related Documents This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices. 1.1.1. SiM3L1xx Reference Manual The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral ...
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... Figure 2.2. Connection Diagram with DC-DC Converter Used and I/O Powered from Battery Figure 2.3 shows a typical connection diagram for the power pins of the SiM3L1xx devices when used with an external radio device like the Silicon Labs EZRadio 6 SiM3L1xx Device VIORF VIO ...
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I/O power pin 4.7, 0.1, and 0.01 uF bypass capacitors required on VBAT/VBATDC input capacitors must be placed as close to the pins as possible. Figure 2.3. Connection Diagram with ...
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SiM3L1xx 3. Electrical Specifications 3.1. Electrical Characteristics All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise. Table 3.1. Recommended Operating Conditions Parameter Operating Supply Voltage on VBAT/VBATDC Operating Supply Voltage on ...
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Table 3.2. Power Consumption Parameter Digital Core Supply Current 1,2,3,4 Normal Mode —Full speed with code executing from flash, peripheral clocks ON 1,2,3,4 Normal Mode —Full speed with code executing from flash, peripheral clocks OFF 1,2,3,4 Normal Mode —Full speed ...
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SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter 1,2,3,4 Power Mode 1 —Full speed with code executing from RAM, peripheral clocks OFF 1,2,3,4 Power Mode 1 —Full speed with code executing from RAM, LDOs powered by dc-dc, peripheral clocks OFF 1,2,3,4 ...
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Table 3.2. Power Consumption (Continued) Parameter 1,2,4,5 Power Mode 4 —Slower clock speed with code executing from flash, peripheral clocks ON 1,2,4,5 Power Mode 5 —Slower clock speed with code executing from RAM, peripheral clocks ON 1,2,4,5 Power Mode 6 ...
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SiM3L1xx Table 3.2. Power Consumption (Continued) Parameter 6 LCD0 , All (4 x 40) segments active Advanced Capture Counter (ACCTR0), LC Single-Ended Mode, Relative to Sampling Fre- 8 quency Advanced Capture Counter (ACCTR0), LC Dual or Quadrature Mode, Relative to ...
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Table 3.2. Power Consumption (Continued) Parameter External Oscillator (EXTOSC0) SARADC0 Temperature Sensor Internal SAR Reference VREF0 Comparator 0 (CMP0), Comparator 1 (CMP1) 7 IDAC0 Voltage Supply Monitor (VMON0) Flash Current on VBAT Write Operation Erase Operation Notes: 1. Currents are ...
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SiM3L1xx Table 3.3. Power Mode Wake Up Times Parameter Power Mode Wake Time Power Mode 3 Fast Wake Time Power Mode 8 Wake Time Notes: 1. Wake times are specified as the time from the wake source ...
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Table 3.5. On-Chip Regulators Parameter DC-DC Buck Converter Input Voltage Range Input Supply to Output Voltage Differ- ential (for regulation) Output Voltage Range Output Voltage Accuracy Output Current 1 Inductor Value Inductor Current Rating Output Capacitor Value 2 Input Capacitor ...
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SiM3L1xx Table 3.5. On-Chip Regulators (Continued) Parameter 5 Memory LDO Output Setting Digital LDO Output Setting Analog LDO Output Setting During 6 Normal Operation Notes: 1. See reference manual for recommended inductors. 2. Recommended: X7R or X5R ceramic capacitors with ...
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Table 3.6. Flash Memory Parameter Write Time Erase Time Endurance (Write/Erase Cycles) Retention* *Note: Additional Data Retention Information is published in the Quarterly Quality and Reliability Report. Symbol Test Condition t One 16-bit Half Word WRITE t One Page ERASE ...
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SiM3L1xx Table 3.7. Internal Oscillators Parameter Phase-Locked Loop (PLL0OSC) Calibrated Output Frequency (Free-running output mode, RANGE = 2) Power Supply Sensitivity (Free-running output mode, RANGE = 2) Temperature Sensitivity (Free-running output mode, RANGE = 2) Adjustable Output Frequency Range Lock ...
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Table 3.7. Internal Oscillators (Continued) Parameter RTC0 Oscillator (RTC0OSC) Missing Clock Detector Trigger Frequency RTC External Input CMOS Clock Frequency RTC Robust Duty Cycle Range Table 3.8. External Oscillator Parameter External Input CMOS Clock Frequency External Crystal Frequency External Input ...
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SiM3L1xx Table 3.9. SAR ADC Parameter Resolution Supply Voltage Requirements (VBAT) Throughput Rate (High Speed Mode) Throughput Rate (Low Power Mode) Tracking Time SAR Clock Frequency Conversion Time Sample/Hold Capacitor Input Pin Capacitance Input Mux Impedance Voltage Reference Range Input ...
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Table 3.9. SAR ADC (Continued) Parameter Offset Temperature Coefficient Slope Error Dynamic Performance (10 kHz Sine Wave Input 1dB below full scale, Max throughput) Signal-to-Noise Signal-to-Noise Plus Distortion Total Harmonic Distortion (Up to 5th Harmonic) Spurious-Free Dynamic Range *Note: Absolute ...
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SiM3L1xx Table 3.10. IDAC Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity (Guaranteed Monotonic) Output Compliance Range Full Scale Output Current Offset Error Full Scale Error Tempco VBAT Power Supply Rejection Ratio Test Load Impedance ( Dynamic ...
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Table 3.11. ACCTR (Advanced Capture Counter) Parameter LC Comparator Response Time, CMPMD = 11 (Highest Speed) LC Comparator Response Time, CMPMD = 00 (Lowest Power) LC Comparator Positive Hysteresis Mode 0 (CPMD = 11) LC Comparator Negative Hysteresis Mode 0 ...
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SiM3L1xx Table 3.11. ACCTR (Advanced Capture Counter) (Continued) Parameter LC Comparator Positive Hysteresis Mode 3 (CPMD = 00) LC Comparator Negative Hysteresis Mode 3 (CPMD = 00) LC Comparator Input Range (ACCTR0_LCIN pin) LC Comparator Common-Mode Rejection Ratio LC Comparator ...
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Table 3.12. Voltage Reference Electrical Characteristics Parameter Internal Fast Settling Reference Output Voltage Temperature Coefficient Turn-on Time Power Supply Rejection PSRR Internal Precision Reference Valid Supply Range Output Voltage Short-Circuit Current Temperature Coefficient Load Regulation Load Capacitor Turn-on Time Power ...
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SiM3L1xx Table 3.14. Comparator Parameter Response Time, CMPMD = 00 (Highest Speed) Response Time, CMPMD = 11 (Lowest Power) Positive Hysteresis Mode 0 (CPMD = 00) Negative Hysteresis Mode 0 (CPMD = 00) Positive Hysteresis Mode 1 (CPMD = 01) ...
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Table 3.14. Comparator (Continued) Parameter Positive Hysteresis Mode 3 (CPMD = 11) Negative Hysteresis Mode 3 (CPMD = 11) Input Range (CP+ or CP–) Input Pin Capacitance Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Offset Voltage Input Offset Tempco ...
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SiM3L1xx Table 3.16. Port I/O Parameter Output High Voltage (PB0, PB1, PB3, or PB4) Output High Voltage (PB2) Output Low Voltage (any Port I/O 1 pin or RESET ) Input High Voltage (PB0, PB1, PB3, PB4 or RESET) Input High ...
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Thermal Conditions Table 3.17. Thermal Conditions Parameter Thermal Resistance* *Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad. Symbol Test Condition TQFP-80 Packages JA TFBGA-80 Packages QFN-64 Packages TQFP-64 Packages ...
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SiM3L1xx 3.3. Absolute Maximum Ratings Stresses above those listed under Table 3.18 may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated ...
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Precision32™ SiM3L1xx System Overview The SiM3L1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Table 5.1 for specific product feature selection and part ordering numbers. Core: 32-bit ARM Cortex-M3 CPU. ...
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SiM3L1xx peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings. The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in ...
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Power The SiM3L1xx devices include a dc-dc buck converter that can take an input from 1.8–3.8 V and create an output from 1.25–3 addition, SiM3L1xx devices include three low dropout regulators as part of the LDO0 module: ...
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SiM3L1xx Supports synchronizing the regulator switching with the system clock. Automatically limits the peak inductor current if the load current rises beyond a safe limit. Automatically goes into bypass mode if the battery voltage cannot provide sufficient ...
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Power Mode 1 and Power Mode 5 Power Mode 1 and Power Mode 5 are fully operational modes with code executing from RAM. PM5 is the same as PM1, but with the clocks operating at a lower speed. This ...
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SiM3L1xx 4.1.5.6. Power Mode Summary The power modes described above are summarized in Table 4.1. Table 3.2 and Table 3.3 provide more information on the power consumption and wake up times for each mode. Mode Core operating at full ...
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Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0) The Process/Voltage/Temperature monitor consists of two modules (TIMER2 and PVTOSC0) designed to monitor the digital circuit performance of the SiM3L1xx device. The PVT oscillator (PVTOSC0) consists of two oscillators, one operating from the memory ...
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SiM3L1xx 4.2. I/O 4.2.1. General Features The SiM3L1xx ports have the following features: tolerant. Push-pull or open-drain output modes to the VIO or VIORF voltage level. Analog or digital modes. Option for high or ...
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Clocking The SiM3L1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and is derived from one of seven sources: the RTC timer clock (RTC0TCLK), the Low Frequency Oscillator, the Low Power Oscillator, the ...
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SiM3L1xx 4.3.1. PLL (PLL0) The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference frequency. The reference frequency for ...
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Integrated LCD Controller (LCD0) SiM3L1xx devices contain an LCD segment driver and on-chip bias generation that supports static, 2-mux, 3-mux and 4-mux LCDs with 1/2 or 1/3 bias. The on-chip charge pump with programmable output voltage allows software contrast ...
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SiM3L1xx 4.5. Data Peripherals 4.5.1. 10-Channel DMA Controller The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of ...
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Enhanced CRC (ECRC0) The ECRC module is designed to provide hardware calculations for flash memory verification and communications protocols. In addition to calculating a result from direct writes from firmware, the ECRC module can automatically snoop the APB ...
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SiM3L1xx 4.6. Counters/Timers 4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2) Each timer module is independent, and includes the following features: Operation as a single 32-bit or two independent 16-bit timers. Clocking options include the APB clock, the APB clock ...
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Real-Time Clock (RTC0) The RTC0 module includes a 32-bit timer that allows hours of independent time-keeping when used with a 32.768 kHz watch crystal. The RTC0 provides three alarm events in addition to a missing clock ...
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SiM3L1xx 4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0) The SiM3L1xx devices contain a low-power Advanced Capture Counter module that runs from the RTC0 clock domain and can be used with digital inputs, switch topology circuits (reed switches), or with ...
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Communications Peripherals 4.7.1. USART (USART0) The USART uses two signals (TX and RX) to communicate serially with an external device. In addition to these signals, the USART module can optionally use a clock (UCLK) or hardware handshaking (RTS and ...
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SiM3L1xx Multiple loop-back modes supported. Multi-processor communications support. Operates at 9600, 4800, 2400, or 1200 baud in Power Mode 8. 4.7.3. SPI (SPI0, SPI1) SPI 4-wire communication interface that includes a clock, input ...
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Analog 4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0) The SARADC0 module on SiM3L1xx devices implements the Successive Approximation Register (SAR) ADC architecture. The key features of the module are as follows: Single-ended 12-bit and 10-bit modes. Supports an output ...
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SiM3L1xx 4.9. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: The core halts program execution. Module registers are initialized to their ...
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Security The peripherals on the SiM3L1xx devices have a register lock and key mechanism that prevents undesired accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A key sequence must be ...
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... SiM3L1xx 5. Ordering Information – B Family – L (Low Power) Core – M3 (Cortex M3) Silicon Labs Figure 5.1. SiM3L1xx Part Numbering All devices in the SiM3L1xx family have the following features: Core: ARM Cortex-M3 with maximum operating frequency of 50 MHz. ...
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Table 5.1. Product Selection Guide SiM3L167-C-GQ 256 32 160 (4x40) SiM3L167-C-GL 256 32 160 (4x40) SiM3L166-C-GM 256 32 128 (4x32) SiM3L166-C-GQ 256 32 128 (4x32) SiM3L164-C-GM 256 32 SiM3L157-C-GQ 128 32 160 (4x40) SiM3L157-C-GL 128 32 160 (4x40) SiM3L156-C-GM 128 ...
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SiM3L1xx 6. Pin Definitions 6.1. SiM3L1x7 Pin Definitions PB0 PB0.2 PB0.1 3 PB0.0 4 TMS / SWDIO 5 TCK / SWCLK 6 VIO 7 VIORF 8 VDRV 9 VBAT / VBATDC 10 IND 11 VSS / VSSDC 12 ...
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PB0.3 PB0.5 PB0.7 A PB0.2 PB0.4 PB0.6 B VIORF PB0.1 C VDRV PB0.0 VIO D VBAT / TCK / VSS VBATDC SWCLK E TMS / PB4.15 / IND SWDIO TRACECLK F PB4.14 / VDC VSS / VSSDC ...
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SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 Pin Name Type VSS Ground VSSDC Ground (DC- 12 DC) VIO Power (I/ VIORF Power (RF I/O) 8 VBAT/ 10 VBATDC VDRV 9 ...
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Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB0.0 Standard I/O 4 PB0.1 Standard I/O 3 PB0.2 Standard I/O 2 PB0.3 Standard I/O 1 PB0.4 Standard I/O 80 PB0.5 Standard I/O 79 PB0.6 Standard I/O ...
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SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB0.9 Standard I/O 75 PB0.10 Standard I/O 74 PB0.11/ Standard I TDO/SWV JTAG / Serial Wire Viewer PB1.0 Standard I/O 66 PB1.1 Standard I/O ...
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Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB1.8 Standard I/O 58 B10 PB1.9 Standard I/O 57 PB1.10 Standard I/O 56 C10 PB1.11 Standard I/O 55 PB2.0 Standard I/O 54 D10 VIORF PB2.1 Standard I/O ...
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SiM3L1xx Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB3.4 Standard I/O 43 H10 PB3.5 Standard I/O 42 PB3.6 Standard I/O 41 PB3.7 Standard I/O 40 PB3.8 Standard I/O 39 K10 PB3.9 Standard I/O 38 ...
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Table 6.1. Pin Definitions and Alternate Functions for SiM3L1x7 (Continued) Pin Name Type PB4.9 Standard I/O 20 PB4.10 Standard I/O 19 PB4.11/ Standard I ETM3 ETM PB4.12/ Standard I ETM2 ETM PB4.13/ Standard I ...
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SiM3L1xx 6.2. SiM3L1x6 Pin Definitions PB0.2 1 PB0.1 2 PB0.0 3 SWDIO 4 SWCLK 5 VIO 6 VIORF / VDRV 7 VBAT / VBATDC 8 IND 9 VSS / VSSDC 10 VDC 11 PB4.12 / TRACECLK 12 PB4.11 / ETM0 ...
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PB0.2 2 PB0.1 3 PB0.0 4 SWDIO 5 SWCLK 6 VIO 7 VIORF / VDRV 8 VBAT / VBATDC 9 IND 10 VSS / VSSDC 11 VDC 12 PB4.12 / TRACECLK 13 PB4.11 / ETM0 14 PB4.10 / ETM1 ...
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SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 Pin Name Type VSS Ground 10 41 VSSDC Ground (DC-DC) 10 VIO Power (I/O) 6 VIORF / Power (RF I/O) 7 VDRV VBAT / 8 VBATDC VDC 11 VLCD Power ...
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Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB0.2 Standard I/O 1 PB0.3 Standard I/O 64 PB0.4 Standard I/O 63 PB0.5 Standard I/O 62 PB0.6 Standard I/O 61 PB0.7 Standard I/O 60 PB0.8 Standard I/O ...
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SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB1.1 Standard I/O 52 PB1.2 Standard I/O 51 PB1.3 Standard I/O 50 PB1.4 Standard I/O 49 PB1.5 Standard I/O 48 PB1.6 Standard I/O 47 PB1.7 Standard ...
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Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB2.5 Standard I/O 39 PB2.6 Standard I/O 38 PB2.7 Standard I/O 37 PB3.0 Standard I/O 36 PB3.1 Standard I/O 35 PB3.2 Standard I/O 34 PB3.3 Standard I/O ...
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SiM3L1xx Table 6.2. Pin Definitions and Alternate Functions for SiM3L1x6 (Continued) Pin Name Type PB4.0 Standard I/O 24 PB4.1 Standard I/O 23 PB4.2 Standard I/O 22 PB4.3 Standard I/O 21 PB4.4 Standard I/O 20 PB4.5 Standard I/O 19 PB4.6 Standard ...
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SiM3L1x4 Pin Definitions PB0.1 1 PB0 SWDIO SWCLK 4 VIO 5 VIORF / VDRV 6 VBAT / VBATDC 7 IND 8 VSS / VSSDC 9 VDC 10 40 pin QFN (Top View) VSS Figure 6.5. SiM3L1x4-GM Pinout ...
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SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 Pin Name Type VSS Ground VSSDC Ground (DC-DC) VIO Power (I/O) VIORF / Power (RF I/O) VDRV VBAT / VBATDC VDC IND DC-DC Inductor RESET Active-low Reset SWCLK Serial Wire ...
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Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB0.2 Standard I/O PB0.3 Standard I/O PB0.4 Standard I/O PB0.5 Standard I/O PB0.6/SWV Standard I/O /Serial Wire Viewer PB0.7 Standard I/O PB0.8 Standard I/O PB0.9 Standard I/O ...
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SiM3L1xx Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB2.1 Standard I/O PB2.2 Standard I/O PB2.3 Standard I/O PB2.4 Standard I/O PB2.5 Standard I/O PB2.6 Standard I/O PB2.7 Standard I/O PB3.0 Standard I/O PB3.1 Standard ...
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Table 6.3. Pin Definitions and Alternate Functions for SiM3L1x4 (Continued) Pin Name Type PB3.6 Standard I/O PB3.7 Standard I/O PB3.8 Standard I/O PB3.9 Standard I/O 14 VIO XBR0 13 VIO XBR0 12 VIO 11 VIO Rev ...
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SiM3L1xx 6.4. TQFP-80 Package Specifications Figure 6.6. TQFP-80 Package Drawing 74 Rev 0.5 ...
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Table 6.4. TQFP-80 Package Dimensions Dimension Min A — A1 0.05 A2 0.95 b 0. 0.45 L1 0° aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters ...
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SiM3L1xx Figure 6.7. TQFP-80 Landing Diagram Table 6.5. TQFP-80 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the ...
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TQFP-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.4.2. TQFP-80 Stencil Design ...
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SiM3L1xx 6.5. TFBGA-80 Package Specifications Figure 6.8. TFBGA-80 Package Drawing 78 E Øb E1 Rev 0 ...
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Table 6.6. TFBGA-80 Package Dimensions Dimension Min A — A1 0.16 A2 0.84 b 0.25 c 0.32 D 5.40 E 5.40 E1 — D1 — e — aaa bbb ddd eee fff Notes: 1. All dimensions shown are in millimeters ...
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SiM3L1xx Figure 6.9. TFBGA-80 Landing Diagram Table 6.7. TFBGA-80 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
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TFBGA-80 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.5.2. TFBGA-80 Stencil Design ...
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SiM3L1xx 6.6. QFN-64 Package Specifications Figure 6.10. QFN-64 Package Drawing Table 6.8. QFN-64 Package Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless ...
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Figure 6.11. QFN-64 Landing Diagram Table 6.9. QFN-64 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. ...
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SiM3L1xx 6.6.1. QFN-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.6.2. QFN-64 Stencil ...
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TQFP-64 Package Specifications Figure 6.12. TQFP-64 Package Drawing Rev 0.5 SiM3L1xx 85 ...
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SiM3L1xx Table 6.10. TQFP-64 Package Dimensions Dimension aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ...
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Figure 6.13. TQFP-64 Landing Diagram Table 6.11. TQFP-64 Landing Diagram Dimensions Dimension Min C1 11.30 C2 11. 0.20 Y 1.40 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design ...
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SiM3L1xx 6.7.1. TQFP-64 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.7.2. TQFP-64 Stencil ...
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QFN-40 Package Specifications Figure 6.14. QFN-40 Package Drawing Table 6.12. QFN-40 Package Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise ...
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SiM3L1xx Figure 6.15. QFN-40 Landing Diagram Table 6.13. QFN-40 Landing Diagram Dimensions Dimension Notes: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum ...
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QFN-40 Solder Mask Design All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µm minimum, all the way around the pad. 6.8.2. QFN-40 Stencil Design ...
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SiM3L1xx 7. Revision Specific Behavior This chapter describes any differences between released revisions of the device. 7.1. Revision Identification The Lot ID Code on the top side of the device package can be used for decoding device revision information. Figures ...
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TFBGA-80 SiM3L 167 CCS701 1221 Figure 7.3. SiM3L1x7-GL and SiM3L1x4-GM Revision Information Rev 0.5 SiM3L1xx QFN-40 SiM3L 164 CCS701 1221 This character identifies the device revision 93 ...
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SiM3L1xx OCUMENT HANGE IST Revision 0.4 to Revision 0.5 Changed 50 nA bullet on front overview to say PM8. Updated Figure 4.4, “SiM3L1xx Reset Sources Block Diagram,” on page 50. Table ...
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... Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog- intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. ...