UPMU-M3L1xLCD-B-EK Silicon Labs, UPMU-M3L1xLCD-B-EK Datasheet - Page 47

• Manufacturer Part Number: UPMU-M3L1xLCD-B-EK
• Description: Daughter Cards & OEM Boards UDP SiM3L1xx MCU Card (with LCD)
• Manufacturer: Silicon Labs

Specifications of UPMU-M3L1xLCD-B-EK

• Product: MCU Cards
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Description/function: MCU Card (with Static LCD) to use with UDP Motherboard
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Tool Is For Evaluation Of: SiM3L1xx
• For Use With: SiM3L1xx

4.7. Communications Peripherals
4.7.1. USART (USART0)
The USART uses two signals (TX and RX) to communicate serially with an external device. In addition to these
signals, the USART module can optionally use a clock (UCLK) or hardware handshaking (RTS and CTS).
The USART module provides the following features:
4.7.2. UART (UART0)
The low-power UART uses two signals (TX and RX) to communicate serially with an external device.
The UART0 module can operate in PM8 mode by taking the clock directly from the RTC0 time clock (RTC0TCLK)
and running from the low power mode charge pump. This will allow the system to conserve power while
transmitting or receiving UART traffic. The UART supports standard baud-rates of 9600, 4800, 2400 and 1200 in
this low power mode.
The UART0 module provides the following features:
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Independent transmitter and receiver configurations with separate 16-bit baud rate generators.
Synchronous or asynchronous transmissions and receptions.
Clock master or slave operation with programmable polarity and edge controls.
Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX
or RX).
Individual enables for generated clocks during start, stop, and idle states.
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation (with separate enables).
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
IrDA modulation and demodulation with programmable pulse widths.
Smartcard ACK/NACK support.
Parity error, frame error, overrun, and underrun detection.
Multi-master and half-duplex support.
Multiple loop-back modes supported.
Multi-processor communications support.
Independent transmitter and receiver configurations with separate 16-bit baud rate generators.
Asynchronous transmissions and receptions.
Up to 5 Mbaud (TX or RX).
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation (with separate enables).
Independent inversion correction for TX and RX signals.
Parity error, frame error, overrun, and underrun detection.
Half-duplex support.
Rev 0.5
SiM3L1xx
47