IS61LV256-12TLI-TR ISSI, Integrated Silicon Solution Inc, IS61LV256-12TLI-TR Datasheet - Page 7

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IS61LV256-12TLI-TR

Manufacturer Part Number
IS61LV256-12TLI-TR
Description
IC SRAM 256KBIT 12NS 28TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LV256-12TLI-TR

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
256K (32K x 8)
Speed
12ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS62LV256
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
4. Tested with OE HIGH.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. K
12/11/02
Symbol
output loading specified in Figure 1a.
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
t
t
t
t
t
t
t
t
WC
SCE
AW
HA
SA
PWE
SD
HD
(4)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
1-800-379-4774
(1,2,3)
Min.
45
35
25
25
20
0
0
0
-45 ns
(Over Operating Range)
Max.
Min.
70
60
60
55
30
0
0
0
-70 ns
Max.
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
®
7

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