Si87xxSOIC8-KIT Silicon Labs, Si87xxSOIC8-KIT Datasheet - Page 15

• Manufacturer Part Number: Si87xxSOIC8-KIT
• Description: Interface Development Tools SOIC8 Evaluation Kit
• Manufacturer: Silicon Labs
• Type: Isolatorsr

Specifications of Si87xxSOIC8-KIT

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: SI87xxSOIC8

New designs should consider the input circuit configurations of Figure 9, which are more efficient than those of
Figures 7 and 8. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si87xx input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 9B). Additionally, note that the Si87xx propagation
delay and output drive do not significantly change for values of I
4.2. Output Circuit Design and Power Supply Connections
The speed of the open collector circuit is dependent upon the supply, VCC, the pullup resistor, R
modeled by C
R
to ensure proper V
the V
than 0.5 V. Figure 10C illustrates a circuit using the internal 20 k resistor.
Note that GND can be biased at, above, or below ground as long as the voltage on V
maximum of 30 V. V
optimum values for these capacitors depend on load current and the distance between the chip and its power
source. It is recommended that 0.1 and 1 µF bypass capacitors be used to reduce high-frequency noise and
maximize performance. Opto replacement applications should limit their supply voltages to 30 V or less.
L
>350 is recommended to ensure proper V
O
Si87xx
pullup resistor, the enable pin should be referenced to the V
A
VDD
GND
VO
VE
L
. Figure 10 illustrates three common circuit output configurations. For V
8
7
6
5
Control
OL
Input
VCC 3-30 V
EN
DD
levels. If the enable pin is used (see Figure 10B) and two separate supplies power V
S1
decoupling capacitors should be placed as close to the package pins as possible. The
R
C
Figure 9. Si87xx Other Input Circuit Configurations
L
L
+5V
Figure 10. Si87xx Output Circuit Configurations
0.1, 1 µF
R1
S2
Si87xx
1
2
3
4
N/C
N/C
ANODE
CATHODE
B
Si87xx
VDD
GND
OL
Preliminary Rev. 0.5
A
VO
VE
levels. For V
0.1, 1 µF
VCC1 3-30 V
8
7
6
5
EN
VCC2 3-30 V
DD
F
MCU I/O
Port pin
between I
R
C
= 30 V operation, R
DD
L
L
pin because V
R1
F(MIN)
1
2
3
4
Si87xx
N/C
N/C
ANODE
CATHODE
C
and I
VDD
Si87xx
O
GND
VL
VO
B
cannot exceed V
DD
L
F(MAX)
> 2.1 kis recommended
with respect to GND is a
8
7
6
5
VCC 3-30 V
.
DD
= 5 V operation,
R
C
Si87xx
L
L
L
, and the load
DD
0.1, 1 µF
by more
DD
and
15