EVAL-ADXL343Z-M Analog Devices, EVAL-ADXL343Z-M Datasheet - Page 19

• Manufacturer Part Number: EVAL-ADXL343Z-M
• Description: Acceleration Sensor Development Tools EB
• Manufacturer: Analog Devices

Specifications of EVAL-ADXL343Z-M

• Rohs: yes
• Tool Is For Evaluation Of: ADXL343
• Acceleration: 2 g, 4 g, 8 g, 16 g
• Sensing Axis: Triple Axis
• Interface Type: I2C, SPI
• Operating Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Current: 140 uA
• Output Type: Digital
• Product: Evaluation Systems
• Sensitivity: 256 LSB/g, 128 LSB/g, 64 LSB/g, 32 LSG/g
• Factory Pack Quantity: 1

Data Sheet
Overrun
The overrun bit is set when new data replaces unread data.
The precise operation of the overrun function depends on the
FIFO mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATAX, DATAY, and DATAZ registers
(Address 0x32 to Address 0x37). In all other modes, the overrun bit
is set when FIFO is filled. The overrun bit is automatically cleared
when the contents of FIFO are read.
FIFO
The
system with a 32-level FIFO memory buffer that can be used to
minimize host processor burden. This buffer has four modes:
bypass, FIFO, stream, and trigger (see Table 22). Each mode is
selected by the settings of the FIFO_MODE bits (Bits[D7:D6])
in the FIFO_CTL register (Address 0x38).
If use of the FIFO is not desired, the FIFO should be placed in
bypass mode.
Bypass Mode
In bypass mode, FIFO is not operational and, therefore,
remains empty.
FIFO Mode
In FIFO mode, data from measurements of the x-, y-, and z-axes
are stored in FIFO. When the number of samples in FIFO equals
the level specified in the samples bits of the FIFO_CTL register
(Address 0x38), the watermark interrupt is set. FIFO continues
accumulating samples until it is full (32 samples from measurements
of the x-, y-, and z-axes) and then stops collecting data. After FIFO
stops collecting data, the device continues to operate; therefore,
features such as tap detection can be used after FIFO is full. The
watermark interrupt continues to occur until the number of
samples in FIFO is less than the value stored in the samples bits
of the FIFO_CTL register.
Stream Mode
In stream mode, data from measurements of the x-, y-, and z-
axes are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
data as new data arrives. The watermark interrupt continues
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.
ADXL343
contains an embedded memory management
Rev. 0 | Page 19 of 36
Trigger Mode
In trigger mode, FIFO accumulates samples, holding the latest
32 samples from measurements of the x-, y-, and z-axes. After
a trigger event occurs and an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
FIFO keeps the last n samples (where n is the value specified by
the samples bits in the FIFO_CTL register) and then operates in
FIFO mode, collecting new samples only when FIFO is not full.
A delay of at least 5 µs should be present between the trigger event
occurring and the start of reading data from the FIFO to allow
the FIFO to discard and retain the necessary samples. Additional
trigger events cannot be recognized until the trigger mode is
reset. To reset the trigger mode, set the device to bypass mode
and then set the device back to trigger mode. Note that the FIFO
data should be read first because placing the device into bypass
mode clears FIFO.
Retrieving Data from FIFO
The FIFO data is read through the DATAX, DATAY, and DATAZ
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,
and DATAZ registers read data stored in the FIFO. Each time
data is read from the FIFO, the oldest x-, y-, and z-axes data are
placed into the DATAX, DATAY, and DATAZ registers.
If a single-byte read operation is performed, the remaining
bytes of data for the current FIFO sample are lost. Therefore, all
axes of interest should be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that
is, that new data has completely moved into the DATAX, DATAY,
and DATAZ registers), there must be at least 5 µs between the
end of reading the data registers and the start of a new read of
the FIFO or a read of the FIFO_STATUS register (Address 0x39).
The end of reading a data register is signified by the transition
from Register 0x37 to Register 0x38 or by the CS pin going high.
For SPI operation at 1.6 MHz or less, the register addressing
portion of the transmission is a sufficient delay to ensure that
the FIFO has completely popped. For SPI operation greater than
1.6 MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 µs; otherwise, the delay is not sufficient. The total delay
necessary for 5 MHz operation is at most 3.4 µs. This is not a
concern when using I
low enough to ensure a sufficient delay between FIFO reads.
2
C mode because the communication rate is
ADXL343