MT48V4M32LFB5-8:G TR Micron Technology Inc, MT48V4M32LFB5-8:G TR Datasheet - Page 18
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MT48V4M32LFB5-8:G TR
Manufacturer Part Number
MT48V4M32LFB5-8:G TR
Description
IC SDRAM 128MBIT 125MHZ 90VFBGA
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Specifications of MT48V4M32LFB5-8:G TR
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-VFBGA
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
19/8/7ns
Maximum Clock Rate
125MHz
Operating Supply Voltage (typ)
2.5V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 6:
NOTE:
CAS Latency (CL)
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
Burst Definition
Notes:
1. For full-page accesses: y = 512 (x16), y = 256 (x32).
2. For BL = 2, A1–A8 (x16) or A1–A7 (x32) select the block-of-two burst; A0 selects the starting
3. For BL = 4, A2–A8 (x16) or A2–A7 (x32) select the block-of-four burst; A0–A1 select the start-
4. For BL = 8, A3–A8 (x16) or A3–A7 (x32) select the block-of-eight burst; A0–A2 select the
5. For a full-page burst, the full row is selected, and A0–A8 (x16) or A0–A7 (x32) select the
6. Whenever a boundary of the block is reached within a given sequence above, the following
7. For BL = 1, A0–A8 (x16) or A0–A7 (x32) select the unique column to be accessed, and mode
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to 1, 2, or 3 clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQ will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a read command is registered at T0 and the
Burst Length
Full page (y)
column within the block.
ing column within the block.
starting column within the block.
starting column.
access wraps within the block.
register bit M3 is ignored.
2
4
8
n = A0–A8 for x16, A0–
A2
Starting Column
0
0
0
0
1
1
1
1
(location 0–y)
A7 for x32
Address
A1
A1
0
0
1
1
0
0
1
1
0
0
1
1
18
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Type = Sequential
Cn + 3, Cn + 4...,
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
128Mb: x16, x32 Mobile SDRAM
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn + 2,
Cn…
0-1
1-0
©2001 Micron Technology, Inc. All rights reserved.
Register Definition
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0