IS42S16160B-7BLI ISSI, Integrated Silicon Solution Inc, IS42S16160B-7BLI Datasheet - Page 12
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IS42S16160B-7BLI
Manufacturer Part Number
IS42S16160B-7BLI
Description
IC SDRAM 256MBIT 143MHZ 54BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16160B-7TLI-TR.pdf
(62 pages)
Specifications of IS42S16160B-7BLI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-BGA
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16160B-7BLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS42S16160B-7BLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S83200B,
FUNCTIONAL TRUTH TABLE Continued:
Current State
Write Recovering
Write Recovering
with Auto
Precharge
Refresh
Mode Register
Accessing
Note: H=V
12
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
be disabled.
state of that bank.
be disabled.
IH
, L=V
IL
x= V
CS
CS
CS
CS
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
IH
or V
IS42S16160B
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
L
L
L
L
H
H
H
L
RAS
RAS
RAS CAS
RAS
RAS
×
×
IL
, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
CAS
CAS
CAS
CAS
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
L
L
H
H
L
L
H
H
L
×
×
×
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
H
L
H
L
H
L
×
H
L
×
×
WE
WE
WE
WE
WE
×
×
Address
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
OC, BA
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
BA, CA, A10
BA, RA
×
×
×
Integrated Silicon Solution, Inc. — www.issi.com
Command
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL
REF/MRS
Action
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read
Begin new write
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
(3,8,11)
(3)
(3)
(3,11)
(3,11)
(3,11)
(8)
07/28/08
Rev. D