IS61NLF12836A-7.5TQLI ISSI, Integrated Silicon Solution Inc, IS61NLF12836A-7.5TQLI Datasheet - Page 5

• Manufacturer Part Number: IS61NLF12836A-7.5TQLI
• Description: IC SRAM 4MBIT 117MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61NLF12836A-7.5TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 4Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 160mA
• Operating Supply Voltage (min): 3.25V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
119-PIN PBGA PACKAGE CONFIGURATION
Note:
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/28/08
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
C
D
F
G
H
M
N
R
A
B
E
P
T
U
J
K
L
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
V
V
V
V
V
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
NC
NC
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
DQPd
DQPc
DQd
DQd
DQd
DQd
NC
CE2
DQc
DQc
DQc
DQc
V
NC
2
A
A
A
DD
MODE
BWd
BWc
V
V
V
V
V
V
V
V
NC
NC
A
A
A
SS
A
SS
SS
SS
SS
SS
SS
3
SS
ADV
CKE
NC
CLK
V
V
V
WE
OE
A
A
NC
NC
CE
128K x 36 (TOP VIEW)
NC
NC
A
4
DD
DD
DD
1
0
OE
ZZ
MODE
V
V
NC
DQa-DQd
DQPa-Pd
V
*
*
DD
SS
DDQ
BWb
BWa
NC
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
A
A
A
A
5
Output Enable
Power Sleep Mode
Burst Sequence Selection
Power Supply
Ground
No Connect
Data Inputs/Outputs
Parity Data I/O
Output Power Supply
DQPb
DQPa
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
CE2
V
NC
NC
A
A
A
DD
6
V
V
V
V
V
DQb
DQb
DQb
DQb
DQa
DQa
DQa
DQa
NC
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
7
5