IS61NLF12836A-7.5TQLI ISSI, Integrated Silicon Solution Inc, IS61NLF12836A-7.5TQLI Datasheet - Page 8

• Manufacturer Part Number: IS61NLF12836A-7.5TQLI
• Description: IC SRAM 4MBIT 117MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61NLF12836A-7.5TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 36)
• Speed: 117MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 4Mb
• Access Time (max): 7.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 117MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 160mA
• Operating Supply Voltage (min): 3.25V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
PIN CONFIGURATION
100-Pin TQFP
PIN DESCRIPTIONS
8
A0, A1
A
CLK
ADV
BWa-BWd
WE
CKE
Vss
NC
DQPc
DQPd
V
V
V
V
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
V
DDQ
Vss
Vss
DDQ
Vss
DDQ
Vss
Vss
DDQ
NC
NC
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
Ground for Core
Not Connected
128K x 36
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
V
Vss
DQb
DQb
DQb
DQb
Vss
V
DQb
DQb
Vss
NC
V
ZZ
DQa
DQa
V
Vss
DQa
DQa
DQa
DQa
Vss
V
DQa
DQa
DQPa
DDQ
DDQ
DD
DDQ
DDQ
CE, CE2, CE2 Synchronous Chip Enable
OE
DQa-DQd
DQPa-DQPd
MODE
V
V
V
ZZ
DQPb
V
V
V
V
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DD
SS
DDQ
DDQ
DDQ
V
DDQ
DDQ
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DD
Integrated Silicon Solution, Inc. — www.issi.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Output Enable
Synchronous Data Input/Output
Parity Data I/O
Burst Sequence Selection
+3.3V/2.5V Power Supply
Ground for output Buffer
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
256K x 18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
05/28/08
A
NC
NC
V
Vss
NC
DQPa
DQa
DQa
Vss
V
DQa
DQa
Vss
NC
V
ZZ
DQa
DQa
V
Vss
DQa
DQa
NC
NC
Vss
V
NC
NC
NC
DDQ
DDQ
DD
DDQ
DDQ
Rev. C