IS61NLF51218A-7.5TQI ISSI, Integrated Silicon Solution Inc, IS61NLF51218A-7.5TQI Datasheet

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IS61NLF51218A-7.5TQI

Manufacturer Part Number
IS61NLF51218A-7.5TQI
Description
IC SRAM 9MBIT 117MHZ 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc

Specifications of IS61NLF51218A-7.5TQI

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (512K x 18)
Speed
117MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
256K x 36 and 512K x 18
9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
• Interleaved or linear burst sequence control using
• Three chip enables for simple depth expansion
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
• Power supply:
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
02/11/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure
of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
data and control
MODE input
and address pipelining
ball PBGA packages
NVF: V
NLF: V
Symbol
t
t
KC
KQ
DD
DD
3.3V (± 5%), V
2.5V (± 5%), V
Parameter
Clock Access Time
Cycle Time
Frequency
DDQ
DDQ
3.3V/2.5V (± 5%)
2.5V (± 5%)
133
6.5
6.5
7.5
1-800-379-4774
DESCRIPTION
The 9 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 36 bits and 512K words by 18
bits, fabricated with
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
A burst mode pin (MODE) defines the order of the burst
117
7.5
7.5
8.5
ISSI
Units
MHz
ns
ns
's advanced CMOS technology.
FEBRUARY 2011
1

Related parts for IS61NLF51218A-7.5TQI

IS61NLF51218A-7.5TQI Summary of contents

Page 1

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 256K x 36 and 512K x 18 9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • ...

Page 2

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A BLOCK DIAGRAM ADDRESS x 36: A [0:17] or REGISTER x 18: A [0:18] CLK CONTROL LOGIC K CKE CE CE2 CE2 CONTROL } ADV REGISTER WE BWŸ X (X= a- DQx/DQPx 2 A2-A17 or A2-A18 MODE BURST ADDRESS A0-A1 A'0-A'1 COUNTER WRITE WRITE ADDRESS ADDRESS REGISTER REGISTER CONTROL LOGIC Integrated Silicon Solution, Inc. — ...

Page 3

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A Bottom View 119-Ball BGA Integrated Silicon Solution, Inc. — www.issi.com — Rev. E 02/11/2011 Bottom View 165-Ball 15mm BGA 1-800-379-4774 3 ...

Page 4

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A PIN CONFIGURATION — 256K CE2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd DQd V DDQ N DQPd NC V DDQ MODE NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 5

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 119-PIN PBGA PACKAGE CONFIGURATION DDQ DQc DQPc D E DQc V F DDQ DQc G DQc DDQ K DQd DQd L DQd DQd V DQd M DDQ N DQd DQd DQd DQPd TMS DDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 6

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 165-PIN PBGA PACKAGE CONFIGURATION CE2 DDQ DQb DDQ V DQb E NC DDQ V F DDQ NC DQb V DDQ G NC DQb DDQ DQb DQb DDQ DQb DDQ V M DQb NC DDQ DQPb DDQ MODE Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 7

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 119-PIN PBGA PACKAGE CONFIGURATION DDQ DQb DDQ DQb J V DDQ K DQb NC L DQb V DQb M DDQ DQb N NC DQPb TMS DDQ Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. ...

Page 8

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A PIN CONFIGURATION 100-Pin TQFP 100 DQPc 1 2 DQc DQc DDQ 5 Vss 6 DQc 7 DQc 8 DQc 9 DQc 10 Vss 11 V DDQ 12 DQc 13 DQc Vss 18 DQd 19 DQd 20 V DDQ 21 Vss 22 DQd 23 DQd 24 DQd 25 DQd 26 Vss 27 V DDQ 28 DQd DQd 29 DQPd 256K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs ...

Page 9

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A STATE DIAGRAM BEGIN READ READ READ BURST BURST BURST READ SYNCHRONOUS TRUTH TABLE Address Operation Used Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read External Address Continue Burst Read Next Address NOP/Dummy Read External Address ...

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... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H L Read L Write L Deselected L Notes means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. ...

Page 11

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A WRITE TRUTH TABLE (x36 Operation READ H WRITE BYTE a L WRITE BYTE b L WRITE BYTE c L WRITE BYTE d L WRITE ALL BYTEs L WRITE ABORT/NOP L Notes : 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. ...

Page 12

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A LINEAR BURST ADDRESS TABLE A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative OUT V Voltage Relative for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

Page 13

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A OPERATING RANGE (IS61NVFx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 14

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 15

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 16

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ t (2,3) Clock High to Output High-Z ...

Page 17

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SLEEP MODE active to input ignored PDS t ZZ inactive to input sampled PUS t ZZ active to SLEEP current ZZI t ZZ inactive to exit SLEEP current RZZI SLEEP MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI ...

Page 18

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A READ CYCLE TIMING CLK t t ADVS ADVH ADV Address WRITE t SE CKE t t CES CEH OEQ t OEHZ t OEHZ Data Out Q1-1 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L ...

Page 19

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A WRITE CYCLE TIMING t KH CLK t ADV Address A1 A2 WRITE CKE CE OE Data In D1-1 t OEHZ Data Out Q0-4 NOTES: WRITE = L means and BWx = and BWX = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — ...

Page 20

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A SINGLE READ/WRITE CYCLE TIMING CLK CKE Address WRITE CE ADV OE t OEQ t OELZ Data Out Data In D2 NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 21

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A CKE CKE CKE OPERATION TIMING CKE CKE CLK CKE Address A1 WRITE CE ADV KQLZ Data Out Q1 Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 22

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A OPERATION TIMING CE CE CLK CKE A1 A2 Address WRITE CE ADV OE t OEQ t OELZ Q1 Q2 Data Out Data In NOTES: WRITE = L means and BWx = means CE1 = L, CE2 = H and CE2 = means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = KQHZ KQ t KQLZ ...

Page 23

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61NLFX and IS61NVFX have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accor- dance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. ...

Page 24

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...

Page 25

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149 ...

Page 26

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A INSTRUCTION CODES Code Instruction 000 EXTEST 001 IDCODE 010 SAMPLE-Z 011 RESERVED 100 SAMPLE/PRELOAD 101 RESERVED 110 RESERVED 111 BYPASS TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 0 26 Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO ...

Page 27

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH1 V Output HIGH Voltage OH2 V Output LOW Voltage OL1 V Output LOW Voltage OL2 V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current X Notes: 1. All Voltage referenced to Ground. ...

Page 28

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A TAP AC TEST CONDITIONS (2.5V/3.3V) Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig TAP TIMING 1 t THTH TCK t MVTH TMS t DVTH TDI TDO 28 TAP Output Load Equivalent ...

Page 29

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M 33 14 DQa 11L 34 15 DQa 11K 35 16 DQa 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 ...

Page 30

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 30 Signal Bump Signal Name ...

Page 31

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 119 BOUNDARY SCAN ORDER (256K X 36) Integrated Silicon Solution, Inc. — www.issi.com — Rev. E 02/11/2011 1-800-379-4774 31 ...

Page 32

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 119 BOUNDARY SCAN ORDER (512K X 18) 32 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 02/22/2011 ...

Page 33

... Order Part Number 256Kx36 IS61NLF25636A-6.5TQI IS61NLF25636A-6.5B2I IS61NLF25636A-6.5B3I IS61NLF25636A-7.5TQI IS61NLF25636A-7.5TQLI IS61NLF25636A-7.5B2I IS61NLF25636A-7.5B2LI IS61NLF25636A-7.5B3I 512Kx18 IS61NLF51218A-6.5TQI IS61NLF51218A-6.5B2I IS61NLF51218A-6.5B3I IS61NLF51218A-7.5TQI IS61NLF51218A-7.5TQLI IS61NLF51218A-7.5B2I IS61NLF51218A-7.5B3I 1-800-379-4774 Package 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA ...

Page 34

... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Access Time 6.5 7.5 6.5 7.5 Industrial Range: -40°C to +85°C Access Time 6.5 7.5 6.5 7 2.5V/V = 2.5V) DD DDQ Order Part Number 256Kx36 IS61NVF25636A-6.5TQ IS61NVF25636A-6.5B2 IS61NVF25636A-6.5B3 IS61NVF25636A-7.5TQ IS61NVF25636A-7.5B2 IS61NVF25636A-7.5B3 512Kx18 IS61NVF51218A-6.5TQ IS61NVF51218A-6.5B2 IS61NVF51218A-6 ...

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... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A Integrated Silicon Solution, Inc. — www.issi.com — Rev. E 02/11/2011 1-800-379-4774 35 ...

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... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A 36 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 02/22/2011 ...

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... IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A Integrated Silicon Solution, Inc. — www.issi.com — Rev. E 02/11/2011 1-800-379-4774 37 ...

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