IS42S32160A-75BL-TR ISSI, Integrated Silicon Solution Inc, IS42S32160A-75BL-TR Datasheet

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IS42S32160A-75BL-TR

Manufacturer Part Number
IS42S32160A-75BL-TR
Description
IC SDRAM 512MBIT 133MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS42S32160A-75BL-TR

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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IS42S32160A-75BL-TR
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ISSI, Integrated Silicon Solution Inc
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Part Number:
IS42S32160A-75BL-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
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4M Words x 32 Bits x 4 Banks (512-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto precharge
· Clock rate: 133 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (4M x 32bit x 4bank)
· Programmable Mode
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 8K refresh cycles/64ms
· 8K refresh cycles/32ms for Industrial grade
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package: 8x13mm, 90 Ball LF-BGA, Ball pitch 0.8mm,
· Pb-free package is available.
· Available in Industrial Temperature
Ball size 0.45mm
IS42S32160A
Integrated Silicon Solution, Inc.
Rev. 00E
07/21/09
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
DESCRIPTION
The ISSI IS42S32160A is a high-speed CMOS
configured as a quad 4M x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
It is internally configured by stacking two 256Mb,
16 Meg x 16 devices. Each of the 4M x 32 bit banks is
organized as 8192 rows by 512 columns by 32 bits.
Read and write accesses start at a selected locations
in a programmed sequence. Accesses begin with
the registration of a BankActive command which is
then followed by a Read or Write command.
The ISSI IS42S32160A provides for programmable
Read or Write burst lengths of 1,2,4,8,or full page, with
a burst termination operation. An auto precharge
function may be enable to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.The refresh functions, either Auto or
Self Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
PRELIMINARY INFORMATION
JULY 2009
1

IS42S32160A-75BL-TR Summary of contents

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... Rev. 00E 07/21/09 PRELIMINARY INFORMATION JULY 2009 DESCRIPTION The ISSI IS42S32160A is a high-speed CMOS configured as a quad DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK internally configured by stacking two 256Mb, 16 Meg x 16 devices. Each of the bit banks is organized as 8192 rows by 512 columns by 32 bits ...

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... IS42S32160A FUNCTIONAL BLOCK DIAGRAM 16 Meg x 16 SDRAM CLK CKE CS COMMAND RAS DECODER CAS & CLOCK WE MODE GENERATOR REGISTER 13 A10 A12 A11 ROW A0 ADDRESS BA0 LATCH BA1 13 COLUMN ADDRESS LATCH 9 BURST COUNTER COLUMN ADDRESS BUFFER Function Block Diagram – 16Meg x 32 SDRAM ...

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... IS42S32160A PIN DESCRIPTIONS Table 1.Pin Details of IS42S32160A Symbol Type Description CLK Input Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn- ...

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... IS42S32160A PIN CONFIGURATION PACKAGE CODE BALL LF-BGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...

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... IS42S32160A Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth table for the operation commands. Table 2.Truth Table (Note (1),(2)) Command State CKEn-1 CKE BankActivate Idle H (3) BankPrecharge Any H PrechargeAll Any H Write Active ...

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... IS42S32160A I Commands 1 BankActivate (RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A12 =Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the row address A12 at the time of this command,the selected row access is initiated.The read or write operation in the same bank can occur after a time delay of tRCD(min ...

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... IS42S32160A 3 PrechargeAll command (RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”) The Precharge All command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. ...

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... IS42S32160A T0 T1 CLK COMMAND READ A NOP CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s Burst Read Operation(Burst Length =4,CAS#Latency =2,3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length ...

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... IS42S32160A T0 T1 CLK COMMAND NOP READ A DQ’s : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 tCK2, DQs : "H" or "L" Read to Write Interval (Burst Length = 4,CAS#Latency = CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ’s tCK2, DQs : " ...

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... IS42S32160A CLK Bank, ADDRESS Col A COMMAND READ A NOP CAS# latency=2 t CK2 , DQ s CAS# latency=3 t CK3 , DQ s Read to Precharge (CAS#Latency =2,3) 5 Write command (RAS#=”H”,CAS#=”L”,WE#=”L”,BS =Bank,A10 =”L”,A0-A8 =Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank ...

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... IS42S32160A CLK COMMAND NOP WRITEA WRITEB 1 Clk Interval DIN A 0 DIN B 0 DQ’s Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure) ...

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... IS42S32160A 6 Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. ...

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... IS42S32160A I WRITE with Auto Precharge · Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m ...

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... IS42S32160A 7 Mode Register Set command (RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A12-A0 =Register Data) The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications.The default values of the Mode Register after power-up are undefined ...

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... I IS42S32160A T0 T1 CLK t CK2 CKE CS# RAS# CAS# WE# ADDR. DQM Hi-Z DQ Precharge All The mode register is divided into various fields depending on functionality. Address BS0,1 A12-A10 Function RFU* *Note:RFU (Reserved for future use)should stay 0 during MRS cycle. Burst Length Field (A2~A0) ¡D ¡D ¡ ...

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... IS42S32160A • Burst Type Field (A3) The Burst Type can be one of two modes,Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave —Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device.The internal column address is varied by the Burst Length as shown in the following table.When the value of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective ...

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... IS42S32160A I • Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to “00”in normal operation • Write Burst Length (A9) This bit is used to select the burst write length. A9 Write Burst Length 0 Burst 1 Single Bit 8 No-Operation command (RAS#=” ...

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... IS42S32160A 10 Device Deselect command (CS#=”H”) The Device Deselect command disables the command decoder so that the RAS#,CAS#,WE# and Address inputs are ignored,regardless of whether the CLK is enabled.This command is similar to the No Operation command. 11 AutoRefresh command (RAS#=”L”,CAS#=”L”,WE#=”H”,CKE =”H”) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before- RAS#(CBR)Refresh in conventional DRAMs ...

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... IS42S32160A I ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Supply Voltage (with respect Supply Voltage for Output (with respect to V DDQ V Input Voltage (with respect Output Voltage (with respect Short circuit output current O P Power Dissipation ( D T Operating Temperature OPT T Storage Temperature STG Notes: 1 ...

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... IS42S32160A D.C. Electrical Characteristics (Recommended Operating Conditions) Description/Test condition Operating Current t t (min), Outputs Open, Input ≥ signal one transition per one cycle Precharge Standby Current in power down mode ≤ 15ns, CKE V (max Precharge Standby Current in power down mode ∞ CKE ...

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... IS42S32160A E AC Electrical Characteristics (Recommended Operating Conditions) Symbol A.C. Parameter t Row cycle time RC (same bank) t Row activate to row activate delay RRD (different banks) t RAS# to CAS# delay RCD (same bank) t Precharge to refresh/row activate command RP (same bank) t Row activate to precharge time RAS (same bank) ...

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... IS42S32160A (N otes Continued) 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall)of Input Signals Reference Level of Input Signals Z0= 50Ω Output LVTTL A.C. Test Load 7. Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope (1 ns) ...

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... IS42S32160A I Timing Waveforms Figure 1.AC Parameters for Write Timing (Burst Length=4,CAS#Latency= CLK CK2 CKE CS# RAS# CAS# WE# BS0 ADDR. RBx DQM t RCD Hi-Z DQ Activate Write with Command Auto Precharge Bank A Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00E 07/21/ T10 T11 ...

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... IS42S32160A Figure 2.AC Parameters for Read Timing (Burst Length=2,CAS#Latency= CLK CKE t IS CS# RAS# CAS# WE# BS0,1 A10 t IS ADD DQM Hi-Z DQ Activate Command Bank CK2 RAx RBx RAx CAx RBx t RRD t RAS t t AC2 t AC2 t HZ RCD t LZ Ax0 Ax1 t OH Read ...

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... IS42S32160A Figure 3.Auto Refresh (CBR)(Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 ADD t DQM Precharge All Auto Refresh Command Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00E 07/21/ T10 T11 T12 T13 T14 RAx RAx Auto Refresh Activate ...

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... IS42S32160A Figure 4.Power on Sequene and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS WE BS0, 1 A10 ADD DQM High Level is Necessary t RP Hi-Z DQ Precharge Command Inputs All Banks must be stable for 200us T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32160A I Figure 5.Self Refresh Entry &Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# RAS# *Note 8 CAS# BS0,1 ADD WE# DQM Hi-Z DQ SelfRefresh Enter Note:To Enter SelfRefresh Mode 1. CS#,RAS#&CAS#with CKE should be low at the same clock cycle. 2. After 1 clock cycle,all the inputs including the system clock can be don ’t care except for CKE. ...

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... IS42S32160A Figure 6.2.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM DQ Hi-Z Activate Read Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32160A I Figure 6.3.Clock Suspension During Burst Read (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD CAx RAx DQM DQ Hi-Z Hi-Z Read Activate Command Command Bank A Bank A Note:CKE to CLK disable/enable =1 clock Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

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... IS42S32160A Figure 7.2.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM Hi-Z DQ DAx0 Clock Suspend Activate Command Bank A Write Command Bank A Note:CKE to CLK disable/enable =1 clock T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32160A I Figure 7.3.Clock Suspension During Burst Write (Using CKE) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM DQ Hi-Z DAx0 Clock Suspend Activate ...

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... IS42S32160A Figure 8.Power Down Mode and Clock Mask (Burst Lenght=4, CAS#Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx ADD DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down Mode Entry T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...

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... IS42S32160A Figure 9.2.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw ADD RAw CAw DQM Hi-Z DQ Activate Read Command Command ...

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... IS42S32160A Figure 9.3.Random Column Read (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAw ADD RAw CAw DQM Hi-Z DQ Activate Read Command Command ...

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... IS42S32160A Figure 10.2.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 ADD CBw RBw DQM Hi-Z DQ DBw0 DBw1 DBw2 DBw3 ...

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... IS42S32160A Figure 10.3.Random Column Write (Page within same Bank) (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw ADD RBw DQM Hi-Z DBw0 DQ Activate Command Command Bank A ...

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... IS42S32160A Figure 11.3.Random Row Read (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx A10 RBx CBx ADD t t RCD AC3 DQM Hi-Z DQ Activate Read ...

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... IS42S32160A Figure 12.2.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...

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... IS42S32160A Figure 12.3.Random Row Write (Interleaving Banks) (Burst Length=8,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx ADD t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 ...

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... IS42S32160A Figure 13.2.Read and Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM Hi-Z DQ Read Activate Command Command Bank A Bank A 40 ...

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... IS42S32160A Figure 13.3.Read and Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

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... IS42S32160A Figure 14.2.Interleaving Column Read Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD CAy RAx t t RCD DQM Hi-Z DQ Read Activate Command Command Bank A ...

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... IS42S32160A Figure 14.3.Interleaved Column Read Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD t RCD DQM DQ Hi-Z Read Activate Command Command Bank A Bank A Integrated Silicon Solution, Inc. — ...

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... IS42S32160A Figure 15.2.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD t RCD DQM t RRD Hi-Z DAx0 DAx1 DAx2 DAx3 DQ Write ...

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... IS42S32160A Figure 15.3.Interleaved Column Write Cycle (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx RBw A10 RAx CAx RBw ADD t RCD DQM t > t RRD RRD(min) Hi-Z DQ DAx0 DAx1 DAx2 DAx3 ...

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... IS42S32160A Figure 16.2.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RBx RAx CAx ADD DQM Hi-Z DQ Ax0 Activate Activate ...

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... IS42S32160A Figure 16.3.Auto Precharge after Read Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RBx CAx RAx RBx ADD DQM Hi-Z DQ Activate Activate Command ...

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... IS42S32160A Figure 17.2.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 CAx ADD RAx DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate ...

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... IS42S32160A Figure 17.3.Auto Precharge after Write Burst (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A9 ADD RAx RBx CAx DQM Hi-Z DAx0 DAx1 DAx2 DAx3 ...

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... IS42S32160A Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM Hi-Z DQ Read Activate Activate Command Command ...

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... IS42S32160A Figure 18.3.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM DQ Hi-Z Read Activate Command Command Bank A Bank A Integrated Silicon Solution, Inc. — ...

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... IS42S32160A Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 ADD RAx CAx DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 ...

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... IS42S32160A Figure 19.3.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RAx CAx ADD RBx DQM Hi-Z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx ...

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... IS42S32160A Figure 20.Byte Write Operation (Burst Length=4,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx ADD RAx CAx DQM0 DQM1,2,3 DQ0 - DQ7 DQ8 - DQ15 Read Activate Command ...

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... IS42S32160A Figure 22.Full Page Random Column Read (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T2 2 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAx RBx CAx CBx CAy ADD DQM t t RRD ...

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... IS42S32160A Figure 23.Full Page Random Column Write (Burst Length=Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RAx ADD RBx CAx DQM t t RRD RCD DQ DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 ...

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... IS42S32160A Figure 24.2.Precharge Termination of a Burst (Burst Length=8 or Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD DQM DQ DAx0 DAx1 DAx2 DAx3 Write ...

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... IS42S32160A Figure 24.3.Precharge Termination of a Burst (Burst Length=4,8 or Full Page,CAS#Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx ADD DQM DQ DAx0 Write Activate Command Command ...

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... Industrial Range: -40°C to +85°C Frequency Speed (ns) 133 MHz 7.5 133 MHz 7.5 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00E 07/21/09 Order Part No. Package IS42S32160A-75B 8 x13mm BGA IS42S32160A-75BL 8 x13mm BGA, Lead-free Order Part No. Package IS42S32160A-75BI 8 x13mm BGA IS42S32160A-75BLI 8 x13mm BGA, Lead-free 59 ...

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