IS42S32160A-75BL-TR ISSI, Integrated Silicon Solution Inc, IS42S32160A-75BL-TR Datasheet - Page 22

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IS42S32160A-75BL-TR

Manufacturer Part Number
IS42S32160A-75BL-TR
Description
IC SDRAM 512MBIT 133MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS42S32160A-75BL-TR

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S32160A-75BL-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S32160A
22
6. A.C. Test Conditions
LVTTL Interface
(N otes Continued)
7.
8.
9.
10. Assumed input rise and fall time t
11. Power up Sequence
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
t
If clock rising time is longer than 1 ns,(t
If t
should be added to the parameter.
Power up must be performed in the following sequence.
1) Power must be applied to V
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same
time.
2) After power-up,a pause of 200 seconds minimum is required.Then,it is recom
mended that DQM is held “HIGH”(V
impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
HZ
R
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
Output
or t
LVTTL A.C. Test Load
F
is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
Z0=
50Ω
DD
T
30pF
and V
50Ω
1.4V
(t
DD
R
&t
R
levels)to ensure DQ output is in high
DDQ
F
/2 -0.5)ns should be added to the parameter.
)=1 ns
(simultaneously)when all input signals are held “NOP”state
1.4V
1.4V /1.4V
Reference to the Under Output Load
2.4V /0.4V
1ns
Integrated Silicon Solution, Inc.
Rev. 00E
07/21/09

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