IS42S32160C-6BLI ISSI, Integrated Silicon Solution Inc, IS42S32160C-6BLI Datasheet - Page 15

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IS42S32160C-6BLI

Manufacturer Part Number
IS42S32160C-6BLI
Description
IC SDRAM 512MBIT 166MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S32160C-6BLI

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-BGA
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
WBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
300mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S32160C-6BLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS42S32160C-6BLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S32160C
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/22/09
Column Address
Burst Type Field (A3)
The Burst Type can be one of two modes,Interleave Mode or Sequential Mode.
• Addressing Sequence of Sequential Mode
Burst Length
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,
4, 8, or full page.
*Note:RFU (Reserved for future use)should stay 0 during MRS cycle.
The mode register is divided into various fields depending on functionality.
Address BS0,1 A12-A10
Function
Data n
An internal column address is performed by increasing the address from the column address which is input to the
device.The internal column address is varied by the Burst Length as shown in the following table. When the value
of column address,(n +m),in the table is larger than 255, only the least significant 8 bits are effective.
Full Page: Column address is repeated until terminated.
0
n
RFU*
4 words:
2 words:
8 words:
n+1
1
n+2
2
WBL
A9
n+3
A2
0
0
0
0
1
1
1
1
3
M
A8
Test Mode
A3
0
1
n+4
4
0
0
1
1
0
0
1
1
A1
Sequential
Interleave
Burst Type
A7
n+5
5
0
1
0
1
1
0
1
0
A0
A6
n+6
CAS Latency
6
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Burst Length
A5
n+7
7
A4
-
-
n+255
255
BT
A3
256
n
A2
Burst Length
257
n+1
A1
-
-
A0
15

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