IS42S32160C-6BLI ISSI, Integrated Silicon Solution Inc, IS42S32160C-6BLI Datasheet - Page 7

• Manufacturer Part Number: IS42S32160C-6BLI
• Description: IC SDRAM 512MBIT 166MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32160C-6BLI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-BGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: WBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 300mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks
for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write
command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a
BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on
any clock cycle following a previous Read command (refer to the following figure).
3
4
IS42S32160C
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
01/22/09
PrechargeAll command
(RAS#=”L”, CAS#=”H”, WE#=”L”, BS =Don t care, A10 =”H”)
The Precharge All command precharges all the four banks simultaneously and can be issued even if all banks are
not in the active state. All banks are then switched to the idle state.
Read command
(RAS#=”H”, CAS#=”L”, WE#=”H”, BS =Bank, A10 =”L”, A0-A8 =Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.) before the Read command is issued.During read bursts,
the valid data-out element from the starting column address will be available following the CAS# latency after the
issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer
to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.
The burst length,burst sequence,and CAS# latency are determined by the mode register which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
CAS# latency=2
t CK2 , DQ- s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ- s
READ A
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
T0
NOP
T1
T2
DOUT A 0
NOP
DOUT A 1
NOP
T3
DOUT A 0
DOUT A 1
DOUT A 2
T4
NOP
DOUT A 3
T5
NOP
DOUT A 2
DOUT A 3
T6
NOP
T7
NOP
T8
NOP
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