MT46H64M32L2JG-5:A TR Micron Technology Inc, MT46H64M32L2JG-5:A TR Datasheet
MT46H64M32L2JG-5:A TR
Specifications of MT46H64M32L2JG-5:A TR
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MT46H64M32L2JG-5:A TR Summary of contents
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Mobile LPDDR 168-Ball Package-on-Package (PoP) TI OMAP™ MT46HxxxMxxLxJG Features • Vdd/Vddq = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock cycle • Differential clock inputs ...
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... MT46H32M32LFJG-54 IT:A MT46H32M32LFJG-6:A MT46H32M32LFJG-6 IT:A MT46H64M32L2JG-5:A MT46H64M32L2JG-5 IT:A MT46H64M32L2JG-54:A MT46H64M32L2JG-54 IT:A MT46H64M32L2JG-6:A MT46H64M32L2JG-6 IT:A Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu- meric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www ...
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... General Description The 1Gb Mobile LPDDR die contained within this package is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits internally config- ured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is orga- nized as 8192 rows by 1024 columns by 32 bits ...
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... Address BA0, BA1 register PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR Bank 3 Bank 2 Bank 1 Bank 0 row- Bank 0 address memory latch array and decoder Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column ...
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Ball Assignments and Descriptions Figure 4: 168-Ball VFBGA (x32) Ball Assignments Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 ...
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Figure 5: 168-Ball VFBGA (x16) Ball Assignments DQ12 DNU DNU DQ14 Vddq UDM Vddq B DNU DNU DQ15 Vssq DQ13 UDQS Vssq C DNU DNU D DNU DNU E Vddq Vssq F DNU ...
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Table 3: x16/x32 LPDDR Ball Descriptions x16 Balls x32 Balls W23, W22, V23, V22, W22, V23, V22, U23, U23, U22, T23, T22, R23, U22, T23, T22, R23, R22, R22, P23, P22, N23, N22 P23, P22, N23, N22 AB21, AC21 AB21, ...
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Table 4: Non-Device-Specific Ball Descriptions Shared Balls x16 B12, H22, K2, K22, L2, B12, H22, K2, K22, L2, P2, AA2, AA22, AB5, P2, AA2, AA22, AB5, AB8, AB13, AB14, AB20 AB8, AB13, AB14, AB20 Miscellaneous Balls x16 A20, A21, B20, ...
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Electrical Specifications Table 5: Absolute Maximum Ratings Parameters/Conditions Vdd, Vddq relative to Vss Voltage on any pin relative to Vss Storage temperature range Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. ...
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Device Diagram Figure 6: 168-Ball VFBGA Functional Block Diagram CK# CKE RAS# CAS# WE# Address, BA0, BA1 PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR CS# CK LPDDR Micron Technology, ...
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Package Dimensions Figure 7: 168-Ball VFBGA Seating plane A 0.08 A 168X Ø0.326 Dimensions apply to solder balls post- reflow. Pre-reflow ball is Ø0.3 on Ø0. ...
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Revision History Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...