MT46V256M4P-6T:A Micron Technology Inc, MT46V256M4P-6T:A Datasheet - Page 81
![IC DDR SDRAM 1GBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V256M4P-6T:A
Manufacturer Part Number
MT46V256M4P-6T:A
Description
IC DDR SDRAM 1GBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V256M4P-6T:A
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (256M x 4)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
256Mx4
Density
1Gb
Address Bus
16b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
230mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power-down (CKE Not Active)
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in
progress, from the issuing of a READ or WRITE command, until completion of the
access. Thus a clock suspend is not supported. For READs, an access completion is
defined when the read postamble is satisfied; for WRITEs, when the write recovery time
(
Power-down, as shown in Figure 53 on page 82, is entered when CKE is registered LOW
and all criteria in Table 27 on page 38 are met. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when a
row is active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CK, CK#, and CKE. For
maximum power savings, the DLL is frozen during precharge power-down mode. Exiting
power-down requires the device to be at the same voltage and frequency as when it
entered power-down. However, power-down duration is limited by the refresh require-
ments of the device (
While in power-down, CKE LOW and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, while all other input signals are “Don’t Care.” The power-
down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied one clock
cycle later.
t
WR) is satisfied.
t
REFC).
81
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Operations