M25PE40-VMC6G NUMONYX, M25PE40-VMC6G Datasheet - Page 27

• Manufacturer Part Number: M25PE40-VMC6G
• Description: IC SRL FLSH 4MB 75MHZ 8MLP
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE40-VMC6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25PE40
Table 8.
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W):
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM2), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
signal
W
Table
1
0
1
0
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction (attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM2) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
3.
SRWD
bit
0
0
1
1
Protection modes (T9HX process only, see
Hardware
protected
protected
software
Second
(SPM2)
(HPM)
Mode
Status Register is writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Status Register is
hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Write protection of the
Status Register
Protected area
Protected against
Sector Erase and
Protected against
Sector Erase and
Page Program,
Page Program,
Bulk Erase
Bulk Erase
Table
Important note on page
8.
Memory content
(1)
Unprotected area
Page Program and
Page Program and
Ready to accept
Ready to accept
Sector Erase
Sector Erase
instructions
instructions
Instructions
6)
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(1)