M25PE40-VMC6G NUMONYX, M25PE40-VMC6G Datasheet - Page 37

• Manufacturer Part Number: M25PE40-VMC6G
• Description: IC SRL FLSH 4MB 75MHZ 8MLP
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE40-VMC6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-MLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M25PE40
6.13
Note:
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction is decoded only in the M25PE40 in the T9HX
process (see
The Subsector Erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on Serial Data input (D). Any address inside
the Subsector (see
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is t
initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Subsector Erase (SSE) instruction applied to a subsector that contains a page that is
hardware or software protected is not executed.
Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a Subsector Erase (SSE) cycle is in progress, the
Subsector Erase cycle is interrupted and data may not be erased correctly (see
Device status after a Reset Low
mode and a time of t
Chip Select (S) Low. For the value of t
Section 11: DC and AC
Figure 19. Subsector Erase (SSE) instruction sequence
1. Address bits A23 to A19 are Don’t care.
S
C
D
Important note on page
Table
RHSL
parameters.
0
4) is a valid address for the Subsector Erase (SE) instruction. Chip
is then required before the device can be re-selected by driving
1
2
Instruction
pulse). On Reset going Low, the device enters the Reset
3
4
RHSL
Figure
5
6).
6
see
7
20.
MSB
23 22
Table 24: Timings after a Reset Low pulse
8
9
24-bit address
2
29 30 31
1
0
Instructions
AI12356
Table 12:
SSE
) is
37/62
in