M45PE20-VMP6G NUMONYX, M45PE20-VMP6G Datasheet - Page 9

IC FLASH 2MBIT 75MHZ 8VFQFPN

M45PE20-VMP6G

Manufacturer Part Number
M45PE20-VMP6G
Description
IC FLASH 2MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r

Specifications of M45PE20-VMP6G

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
256K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
25MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M45PE20-VMP6G
Manufacturer:
ST
0
Part Number:
M45PE20-VMP6G
Manufacturer:
ST
Quantity:
20 000
Status Register
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
Table 2. Status Register Format
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M45PE20 features
the following data protection mechanisms:
b7
0
Power On Reset and an internal timer (t
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
Program, Erase and Write instructions are
checked that they consist of a number of clock
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
0
0
0
0
0
WEL
PUW
WIP
b0
)
pulses that is a multiple of eight, before they
are accepted for execution.
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
The Hardware Protected mode is entered
when Write Protect (W) is driven Low, causing
the first 256 pages of memory to become
read-only. When Write Protect (W) is driven
High, the first 256 pages of memory behave
like the other pages of memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions while
the device is not in active use.
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction
completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
M45PE20
9/35

Related parts for M45PE20-VMP6G