N25Q128A13B1240F NUMONYX, N25Q128A13B1240F Datasheet - Page 89

• Manufacturer Part Number: N25Q128A13B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
9.2
S#
C
DQ0
The Reset Enable instruction is entered by driving S low, followed by the instruction code on
serial data input (DQ0). The Reset Memory instruction is entered by driving S low, followed
by the instruction code on DQ0.
Minimum deselection time between the Reset Enable instruction and the Reset Memory
instruction must be set according to the tSHSL2 specification; otherwise, reset software is
not guaranteed.
If a Reset operation is begun while an internal Write, Program, or Erase operation is in
progress or suspended, the internal operation is affected and data might be lost. As soon as
S is driven high after the Reset Memory instruction is issued, the device enters the Reset
mode and a time of tSHSL3 is then required before the device can be reselected by driving
S low. You should exit XiP mode before entering software reset as described in XIP Hold
and Exit.
Figure 43. Reset Enable and Reset Memory Instruction Sequence
DIO-SPI Instructions
In DIO-SPI protocol, instructions, addresses and input/Output data always run in parallel on
two wires: DQ0 and DQ1.
In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock
Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read
NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),
Read Volatile Enhanced Configuration Register (RDVECR) and Multiple I/O Read
Identification (MIORDID) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector
Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),
Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register
(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRVCR),
Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration
Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip
Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is
rejected, and is not executed.
All attempts to access the memory array during a Write Status Register cycle, a Write Non
Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the
internal Write Status Register cycle, Write Non Volatile Configuration Register, Program
0
1
2
Reset Enable
3
4
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
2
Reset Memory
3
©2010 Micron Technology, Inc. All rights reserved.
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5
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Instructions
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