N25Q128A13B1240F NUMONYX, N25Q128A13B1240F Datasheet - Page 91

• Manufacturer Part Number: N25Q128A13B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
Table 24.
Table 25.
9.2.1
Reset Enable
Reset Memory
Instruction
WRNVCR
WRVECR
RDVCR
WRVCR
RDVECR
Instruction
Read Volatile Configuration Register
Write Volatile Configuration Register
Read Volatile Enhanced Configuration
Register
Register
Instruction set: DIO-SPI protocol (page 2 of 2)
1)
2)
Reset Opcodes
Multiple I/O Read Identification protocol
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the DIO-SPI protocol:
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction cannot read the Unique ID code (UID) (17 bytes). For further details on the
manufacturer and device identification codes please refer to
Identification
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit
device identification, stored in the memory, will be shifted out on again in parallel on DQ1
and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode,
and execute instructions.
Write NV Configuration Register
Write Volatile Enhanced Configuration
The number of Dummy Clock cycles is configurable by the user
SSE is only available in devices with Bottom or Top architecture.
–
–
Manufacturer identification (1 byte)
Device identification (2 bytes)
Description
(RDID).
0110 0110
1001 1001
Instruction Code (binary)
0110 0101
1011 0001
1000 0101
1000 0001
0110 0001
Instruction
Code (BIN)
One-byte
Micron Technology, Inc., reserves the right to change products or specifications without notice.
66
99
Instruction Code (hex)
Instruction
B1h
85h
81h
65h
61h
One-byte
(HEX)
Code
Section 9.1.1: Read
©2010 Micron Technology, Inc. All rights reserved.
Address
0
0
0
0
0
bytes
0
Dummy
0
0
0
0
clock
cycle
0
0
Address Bytes
Instructions
2
1
1
1 to
1 to
bytes
Data
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