NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 13
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NAND01GW3B2CN6E
Manufacturer Part Number
NAND01GW3B2CN6E
Description
IC FLASH 1GBIT 48TSOP
Manufacturer
NUMONYX
Specifications of NAND01GW3B2CN6E
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
1G (128M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Cell Type
NAND
Density
1Gb
Access Time (max)
25us
Interface Type
Parallel
Boot Type
Not Required
Address Bus
8b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
128M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NAND01GW3B2CN6E
Manufacturer:
Numonyx
Quantity:
5
Part Number:
NAND01GW3B2CN6E
Manufacturer:
ST
Quantity:
20 000
NAND01G-B2C
2
2.1
Memory array organization
The memory array is made up of two NAND structures where 32 cells are connected in
series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a 2048-byte main area and a spare area of 64 bytes. In
the x16 devices the pages are split into a 1024-word main area and a 32-word spare area.
Refer to
Bad blocks
The NAND flash 2112-byte/1056-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block Information is written prior to shipping (refer to
management
Table 4: Valid blocks
shown include both the bad blocks that are present when the device is shipped and the bad
blocks that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to
Table 4.
Figure 6: Memory array
Density of device
Valid blocks
for more details).
1 Gbit
shows the minimum number of valid blocks in the device. The values
Section 8: Software
organization.
1004
Min
algorithms).
Section 8.1: Bad block
Memory array organization
1024
Max
13/67