NAND01GW3B2CN6E NUMONYX, NAND01GW3B2CN6E Datasheet - Page 26

• Manufacturer Part Number: NAND01GW3B2CN6E
• Description: IC FLASH 1GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND01GW3B2CN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NAND
• Density: 1Gb
• Access Time (max): 25us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

Device operations
Figure 10. Cache read operation
6.3
6.3.1
26/67
R/B
CL
AL
I/O
W
R
30h
Page program
The page program operation is the standard operation to program data to the memory array.
Within a given block, the pages must be programmed sequentially. Random page address
programming is not recommended.
The memory array is programmed by page, however partial page programming is allowed
where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is four. After exceeding this a Block Erase command must be issued before any further
program operations can take place in that page.
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input each page program operation consists of five steps (see
1.
2.
3.
4.
5.
tBLBH1
one bus cycle is required to setup the Page Program (sequential input) command (see
Table
four bus cycles are then required to input the program address (refer to
Table
the data is then loaded into the data registers
one bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R will only start if the data has been loaded in step 3
the P/E/R controller then programs the data into the array.
10)
7)
00h
C1
C2
Random
R1
R2
31h
tBLBHx
D0
...
Dn
Sequential
31h
NAND01G-B2C
Table 6
tBLBHx
Figure
ai14293
and
11):
D0