M29W128GL70N6E NUMONYX, M29W128GL70N6E Datasheet - Page 53

• Manufacturer Part Number: M29W128GL70N6E
• Description: IC FLASH 128MBIT 70NS 56TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W128GL70N6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Package: 56TSOP
• Cell Type: NOR
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 128KByte x 128
• Timing Type: Asynchronous
• Interface Type: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
7.2.1
7.2.2
7.2.3
Status register
The M29W128GH/L has one status register. The various bits convey information and errors
on the current and previous program/erase operation. Bus read operations from any
address within the memory, always read the status register during program and erase
operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations, from the address just programmed, output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from ’0’ to ’1’ when the
program/erase controller has suspended the erase operation.
Figure 8: Data polling
address is the address being programmed or an address within the block being erased.
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During a program/erase operation the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the
operation the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
Figure 9: Data toggle
Error bit (DQ5)
The error bit can be used to identify errors detected by the program/erase controller. The
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the
correct data to the memory. If the error bit is set a Read/Reset command must be issued
flowchart, gives an example of how to use the toggle bit.
flowchart, gives an example of how to use the data polling bit. A valid
Table 20: Status register
bits.
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