CY7C1371D-133AXC Cypress Semiconductor Corp, CY7C1371D-133AXC Datasheet - Page 15
![IC SRAM 18MBIT 133MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1371D-133AXC
Manufacturer Part Number
CY7C1371D-133AXC
Description
IC SRAM 18MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1373D-100AXC.pdf
(33 pages)
Specifications of CY7C1371D-133AXC
Memory Size
18M (512K x 36)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
6.5 ns
Maximum Clock Frequency
133 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
210 mA
Organization
1 M x 18, 512 K x 36
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
3.3 V
Memory Configuration
512K X 36
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2139
CY7C1371D-133AXC
CY7C1371D-133AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1371D-133AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1371D-133AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-FBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
TAP Timing
Document Number: 38-05556 Rev. *I
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
t
TL
3
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is preset HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
UNDEFINED
4
t TDOX
t TDOV
5
6
CY7C1371D
CY7C1373D
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