CY7C1371D-133AXC Cypress Semiconductor Corp, CY7C1371D-133AXC Datasheet - Page 16
![IC SRAM 18MBIT 133MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1371D-133AXC
Manufacturer Part Number
CY7C1371D-133AXC
Description
IC SRAM 18MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1373D-100AXC.pdf
(33 pages)
Specifications of CY7C1371D-133AXC
Memory Size
18M (512K x 36)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
6.5 ns
Maximum Clock Frequency
133 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
210 mA
Organization
1 M x 18, 512 K x 36
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
3.3 V
Memory Configuration
512K X 36
Supply Voltage Range
3.135V To 3.6V
Memory Case Style
TQFP
No. Of Pins
100
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2139
CY7C1371D-133AXC
CY7C1371D-133AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1371D-133AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1371D-133AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
TAP AC Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05556 Rev. *I
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
10. t
11. Test conditions are specified using the load in TAP AC test Conditions. t
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
Parameter
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMS Hold after TCK clock rise
TDI Hold after clock rise
Capture hold after clock rise
[10, 11]
Description
R
/t
F
= 1 ns.
Min
50
20
20
–
–
0
5
5
5
5
5
5
Max
20
10
–
–
–
–
–
–
–
–
–
–
CY7C1371D
CY7C1373D
Page 16 of 33
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback