SST25VF040B-50-4I-QAF Microchip Technology, SST25VF040B-50-4I-QAF Datasheet - Page 5
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SST25VF040B-50-4I-QAF
Manufacturer Part Number
SST25VF040B-50-4I-QAF
Description
IC FLASH SER 4MB 50MHZ SPI 8WSON
Manufacturer
Microchip Technology
Datasheets
1.SST25VF512A-33-4C-SAE.pdf
(2 pages)
2.SST25VF040B-80-4I-SAE.pdf
(33 pages)
3.SST25VF040B-80-4I-QAE.pdf
(33 pages)
Specifications of SST25VF040B-50-4I-QAF
Memory Type
FLASH
Memory Size
4M (512K x 8)
Operating Temperature
-40°C ~ 85°C
Package / Case
8-WSON
Format - Memory
FLASH
Speed
50MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Architecture
Sectored
Interface Type
SPI
Access Time
50 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Memory Organization
Device Operation
Hold Operation
The SST25VF040B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF040B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is
accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
The SST25VF040B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is
high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock
signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock signal.
Figure 3: SPI Protocol
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-
ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
V
If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the
device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 24 for Hold
timing.
IH.
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
4 Mbit SPI Serial Flash
DON T CARE
SST25VF040B
MODE 3
MODE 0
S71295-06-000
1295 SPIprot.0
Data Sheet
IL
02/11
or