AT25640AN-10SU-2.7 Atmel, AT25640AN-10SU-2.7 Datasheet - Page 10

• Manufacturer Part Number: AT25640AN-10SU-2.7
• Description: IC EEPROM 64KBIT 20MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25640AN-10SU-2.7

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT25640AN-10SU2.7

10
AT25080A/160A/320A/640A
Table 3-3.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments.
One-quarter, one-half, or all of the memory segments can be protected. Any of the data within
any selected segment will therefore be read only. The block write protection levels and corre-
sponding status register control bits are shown in
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, t
Table 3-4.
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block-pro-
tected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as
long as the WP pin is held low.
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0–7 are “1”s during an internal write cycle.
Level
1(1/4)
2(1/2)
3(All)
0
BP1
Read Status Register Bit Definition
Block Write Protect Bits
Register Bits
0
0
1
1
Status
Definition
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
See
See
See
Table 3-4 on page 10
Table 3-4 on page 10
Table 3-5 on page 11
BP0
0
1
0
1
AT25080A
03FF
03FF
03FF
None
0300
0200
0000
.
.
.
Array Addresses Protected
Table
AT25160A
07FF
07FF
07FF
None
0600
0400
0000
WC
, RDSR).
3-4.
AT25320A
0FFF
0FFF
0FFF
None
0C00
0800
0000
3347L–SEEPR–06/07
AT25640A
1FFF
1FFF
1FFF
None
1800
1000
0000