AT25640AN-10SU-2.7 Atmel, AT25640AN-10SU-2.7 Datasheet - Page 11

• Manufacturer Part Number: AT25640AN-10SU-2.7
• Description: IC EEPROM 64KBIT 20MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25640AN-10SU-2.7

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT25640AN-10SU2.7

3347L–SEEPR–06/07
Table 3-5.
READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the Serial Output
(SO) pin requires the following sequence. After the CS line is pulled low to select a device, the
read op-code is transmitted via the SI line followed by the byte address to be read (A15
Table
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The read sequence can be continued since the
byte address is automatically incremented and data will continue to be shifted out. When the
highest address is reached, the address counter will roll over to the lowest address allowing the
entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sepa-
rate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a write (WRITE) instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location selected by
the block write protection level. During an internal write cycle, all commands will be ignored
except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15
and the data (D7
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time
immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte of
data is received, the five low-order address bits are internally incremented by one; the high-
order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the
address counter will roll over and the previously written data will be overwritten. The
AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple-
tion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to
reinitiate the serial communication.
WPEN
X
X
0
0
1
1
3-6). Upon completion, any data on the SI line will be ignored. The data (D7
WPEN Operation
–
High
High
D0) to be programmed (see
Low
Low
WP
X
X
WEN
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
AT25080A/160A/320A/640A
Table
3-6). Programming will start after the CS pin
Unprotected
Protected
Protected
Protected
Writeable
Writeable
Writeable
Blocks
Protected
Writeable
Protected
Protected
Protected
Writeable
Register
Status
–
D0) at the
–
A0, see
–
A0)
11