AT45DB041D-SU Atmel, AT45DB041D-SU Datasheet - Page 11

• Manufacturer Part Number: AT45DB041D-SU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 264 B
• Current, Input, Leakage: 1 μA
• Current, Operating: 10 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 to 3.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.8
8. Sector Protection
3595P–DFLASH–09/09
Main Memory Page Program Through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI)
and then programmed into a specified page in the main memory. To perform a main memory
page program through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode,
82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three
address bytes. The address bytes are comprised of 4 don’t care bits, 11 page address bits,
(PA10 - PA0) that select the page in the main memory where data is to be written, and 9 buffer
address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a
main memory page program through buffer for the binary page size (256 bytes), the opcode 82H
for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes
consisting of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the main
memory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in the
buffer to be written. After all address bytes are clocked in, the part will take data from the input
pins and store it in the specified data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS
pin, the part will first erase the selected page in main memory to all 1s and then program the
data stored in the buffer into that memory page. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum time of t
the status register will indicate that the part is busy.
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.
AT45DB041D
EP
. During this time,
11