AT45DB041D-SU Atmel, AT45DB041D-SU Datasheet - Page 4

• Manufacturer Part Number: AT45DB041D-SU
• Description: IC FLASH 4MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB041D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 4Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 264 B
• Current, Input, Leakage: 1 μA
• Current, Operating: 10 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 to 3.4 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4. Memory Array
Figure 4-1.
5. Device Operation
4
SECTOR ARCHITECTURE
AT45DB041D
SECTOR 1 = 256 Pages
SECTOR 2 = 256 Pages
SECTOR 6 = 256 Pages
SECTOR 0b = 248 Pages
SECTOR 7 = 256 Pages
SECTOR 0a = 8 Pages
65,536/67,584 bytes
65,536/67,584 bytes
65,536/67,584
65,536/67,584 bytes
63,488/65,472 bytes
2,048/2,112 bytes
Memory Architecture Diagram
bytes
To provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis. The erase operations can
be performed at the chip, sector, block or page level.
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer
or main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most significant
bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the
datasheet using the terminology BEA8 - BFA0 to denote the 9 address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to desig-
nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte
address within the page.
For the “Power of 2” binary page size (256 bytes), the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to desig-
nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte
address within a page.
SECTOR 0a
BLOCK ARCHITECTURE
Block = 2,048/2,112 bytes
BLOCK 254
BLOCK 255
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
Tables 15-1 through
8 Pages
PAGE ARCHITECTURE
15-7. A valid instruction
Page = 256/264 bytes
PAGE 2,046
PAGE 2,047
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3595P–DFLASH–09/09