MT46V16M16P-6T L:F TR Micron Technology Inc, MT46V16M16P-6T L:F TR Datasheet - Page 56
![IC DDR SDRAM 256MBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V16M16P-6T L:F TR
Manufacturer Part Number
MT46V16M16P-6T L:F TR
Description
IC DDR SDRAM 256MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V16M16CY-5BK_TR.pdf
(93 pages)
Specifications of MT46V16M16P-6T L:F TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
256M (16Mx16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 22:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
Command
BA0, BA1
Address
V
V
DQS
DD
V
CK#
CKE
A10
V
DM
DQ
CK
TT
REF
DD
Q
1
t VTD 1
INITIALIZATION Timing Diagram
Notes:
LVCMOS
LOW level
Power-up: V
T = 200µs
1. V
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com-
4.
5. While programming the operating parameters, reset the DLL with A8 = 1.
(
(
(
(
(
(
(
)
(
)
)
)
)
)
(
(
(
(
(
(
)
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
(
(
)
(
)
(
)
(
)
(
)
(
(
(
)
)
)
)
)
)
)
)
)
)
)
)
)
V
even if V
the V
specified range.
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
mand at Ta0.
t
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
MRD is required before any command can be applied (during MRD time only NOPs or
DD
TT
TT
t IS t IH
t IS
and CK stable
NOP
, and V
T0
is not applied directly to the device; however,
High-Z
High-Z
TT
t IH
t CH
t CK
supply and the input pin. Once initialized, V
DD
REF
/V
t CL
All banks
DD
t IS t IH
≤ V
PRE
T1
Q are 0V, provided a minimum of 42Ω of series resistance is used between
DD
+ 0.3V. Alternatively, V
t RP
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
Load extended
)
)
)
)
)
)
)
mode register
t IS t IH
t IS t IH
t IS t IH
BA0 = 1
BA1 = 0
Code
Code
LMR
Ta0
54
t MRD
(
(
(
(
(
(
(
(
(
)
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
Load mode
register5
Code 3
BA0 = 0
BA1 = 0
Code
LMR
Tb0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t MRD
(
(
(
(
(
(
(
TT
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
may be 1.35V maximum during power-up,
All banks
t IS t IH
PRE
256Mb: x4, x8, x16 DDR SDRAM
Tc0
t
VTD ≥ 0 to avoid device latch-up. V
REF
t RP
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
must always be powered within the
200 cycles of CK4
Td0
AR
Indicates A Break in
Time Scale
©2003 Micron Technology, Inc. All rights reserved.
t RFC
(
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
Te0
AR
t RFC
(
(
(
(
(
(
(
Operations
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
)
)
ACT 2
Don’t Care
Tf0
BA
RA
RA
DD
Q,