PSD813F1A-90JI STMicroelectronics, PSD813F1A-90JI Datasheet - Page 56
![IC FLASH 1MBIT 90NS 52PLCC](/photos/7/24/72493/497-52-plcc_series_sml.jpg)
PSD813F1A-90JI
Manufacturer Part Number
PSD813F1A-90JI
Description
IC FLASH 1MBIT 90NS 52PLCC
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F1A-90U.pdf
(111 pages)
Specifications of PSD813F1A-90JI
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
1M (128K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1976-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PSD813F1A-90JI
Manufacturer:
WSI
Quantity:
10
Company:
Part Number:
PSD813F1A-90JI
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD813F1A
Address In Mode
For microcontrollers that have more than 16 ad-
dress lines, the higher addresses can be connect-
ed to Port A, B, C, and D. The address input can
be latched in the Input Macrocell by the address
strobe (ALE/AS). Any input that is included in the
DPLD equations for the PLD’s Flash, EEPROM, or
SRAM is considered to be an address input.
Data Port Mode
Port A can be used as a data bus port for a micro-
controller with a non-multiplexed address/data
bus. The Data Port is connected to the data bus of
the microcontroller. The general I/O functions are
disabled in Port A if the port is configured as a
Data Port.
Figure 28. Peripheral I/O Mode
56/111
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PSEL
DATA BUS
Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-stateable, bi-directional data buffer
for the microcontroller. Peripheral I/O Mode is en-
abled by setting Bit 7 of the VM Register to a ‘1.’
Figure
D0 - D7
al buffer for the microcontroller data bus if Periph-
eral I/O Mode is enabled. An equation for PSEL0
and/or PSEL1 must be written in PSDabel. The
buffer is tri-stated when PSEL 0 or PSEL1 is not
active.
28
shows how Port A acts as a bi-direction-
PA0 - PA7
AI02886