psd813f1a STMicroelectronics, psd813f1a Datasheet
psd813f1a
Manufacturer Part Number
psd813f1a
Description
Flash In-system Programmable Isp Peripherals For 8-bit Mcus, 5 V
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F1A.pdf
(111 pages)
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FEATURES SUMMARY
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October 2008
This is information on a product still in production but not recommended for new designs.
DUAL BANK FLASH MEMORIES
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–
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16 Kbit SRAM
PLD WITH MACROCELLS
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–
–
27 RECONFIGURABLE I/Os
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ENHANCED JTAG SERIAL PORT
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PAGE REGISTER
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PROGRAMMABLE POWER MANAGEMENT
1 Mbit of Primary Flash Memory (8
Uniform Sectors)
256 Kbit Secondary EEPROM (4 Uniform
Sectors)
Concurrent operation: read from one
memory while erasing and writing the
other
Over 3,000 Gates Of PLD: DPLD and
CPLD
DPLD - User-defined Internal chip-select
decoding
CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
27 individually configurable I/O port pins
that can be used for the following
functions (16 I/O ports configurable as
open-drain outputs):
MCU I/Os
PLD I/Os
Latched MCU address output; and
Special function I/Os
Built-in JTAG-compliant serial port allows
full-chip In-System Programmability (ISP)
Efficient manufacturing allows for easy
product testing and programming
Internal page register that can be used to
expand the microcontroller address space
by a factor of 256.
Flash in-system programmable (ISP) peripherals
Rev 5
Figure 1. Packages
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HIGH ENDURANCE:
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SINGLE SUPPLY VOLTAGE:
–
STANDBY CURRENT AS LOW AS 50µA
Packages are ECOPACK
100,000 Erase/WRITE Cycles of Flash
Memory
10,000 Erase/WRITE Cycles of EEPROM
1,000 Erase/WRITE Cycles of PLD
Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
5V±10% for 5V
for 8-bit MCUs, 5 V
TQFQ64 (U)
PQFP52 (M)
PLCC52 (J)
PSD813F1A
NOT FOR NEW DESIGN
®
1/111
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