psd813f1a STMicroelectronics, psd813f1a Datasheet - Page 41

• Manufacturer Part Number: psd813f1a
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus, 5 V
• Manufacturer: STMicroelectronics

Input Macrocells (IMC)
The CPLD has 24 IMCs, one for each pin on Ports
A, B, and C. The architecture of the IMC is shown
in
configurable, and can be used as a latch, register,
or to pass incoming Port signals prior to driving
them onto the PLD input bus. The outputs of the
IMCs can be read by the microcontroller through
the internal data bus.
The enable for the latch and clock for the register
are driven by a multiplexer whose inputs are a
product term from the CPLD AND array or the
MCU address strobe (ALE/AS). Each product term
output is used to latch or clock four IMCs. Port in-
puts 3-0 can be controlled by one product term
and 7-4 by another.
Configurations for the IMCs are specified by equa-
tions written in PSDabel (see Application Note 55).
Outputs of the IMCs can be read by the MCU via
Figure 19., page
42. The IMCs are individually
the IMC buffer. See the I/O Port section on how to
read the IMCs.
IMCs can use the address strobe to latch address
bits higher than A15. Any latched addresses are
routed to the PLDs as inputs.
IMCs are particularly useful with handshaking
communication applications where two proces-
sors pass data back and forth through a common
mailbox.
figuration where the Master MCU writes to the Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to the Port A IMCs and
the Master can then read the IMCs directly.
Note that the “Slave-Read” and “Slave-wr” signals
are product terms that are derived from the Slave
MCU inputs RD, WR, and Slave_CS.
Figure 20., page 43
shows a typical con-
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