PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet
PSD813F1
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PSD813F1 Summary of contents
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... Flash In-System Programmable (ISP) Peripherals FEATURES SUMMARY Single Supply Voltage: – 5 V±10% for PSD813F1-A – 3.3 V±10% for PSD813F1- 1Mbit of Primary Flash Memory (8 uniform sectors) 256Kbit Secondary EEPROM (4 uniform sectors 16Kbit SRAM Over 3,000 Gates of PLD: DPLD and CPLD ...
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... PLDs .......................................................................................................................................................6 5.4 I/O Ports..................................................................................................................................................7 5.5 Microcontroller Bus Interface ..................................................................................................................7 5.6 JTAG Port ...............................................................................................................................................7 5.7 In-System Programming .........................................................................................................................8 5.8 Power Management................................................................................................................................8 6.0 Development System............................................................................................................................................9 7.0 PSD813F1 Pin Descriptions ...............................................................................................................................10 8.0 PSD813F1 Register Description and Address Offset .........................................................................................14 9.0 PSD813F1 Functional Blocks .............................................................................................................................15 9.1 Memory Blocks .....................................................................................................................................15 9.1.1 Main Flash and Secondary EEPROM ........................................................................................15 9.1.2 SRAM .........................................................................................................................................29 9.1.3 Memory Select Signals...............................................................................................................29 9.1.4 Page Register.............................................................................................................................32 9.2 PLDs .....................................................................................................................................................33 9.2.1 Decode PLD (DPLD) ..................................................................................................................35 9 ...
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... Absolute Maximum Ratings.........................................................................................................................................76 AD/DC Parameters......................................................................................................................................................77 Example of PSD813F Typical Power Calculation at V PSD813F1 DC Characteristics (5 V ± 10% Versions) ........................................................................................80 PSD813F1 AD/DC Parameters – CPLD Timing Parameters (5 V ± 10% versions) .........................................81 PSD813F1V DC Characteristics (3 V Versions) .................................................................................................91 PSD813F1V AC/DC Parameters – CPLD Timing Parameters (3 V versions) .................................................92 Timing Diagrams .......................................................................................................................................................100 Programming .............................................................................................................................................................107 PSD813F1 Pin Assignments ...
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... PSD813F1-A Family iii For additional information, Call 800-832-6974 Fax: 510-657-8495 Web Site: http://www.psdst.com E-mail: ask.psd@st.com Preliminary ...
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... The PSD813F1 family of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a Introduction simple and flexible solution for embedded designs. PSD813F1 devices combine many of the peripheral functions found in MCU based applications: • 1 Mbit of Flash memory • ...
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... Flash ISP via the UART of the host MCU • Memory paging to execute code across several PSD memory pages • Loading, reading, and manipulation of PSD Micro Cells by the MCU The PSD813F1 is available in a 52-pin PLCC package and a 64-pin plastic Thin Quad Flatpack (TQFP) package. 2 Preliminary ...
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... Internal programmable Power Management Unit (PMU) that supports a low power mode called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD813F1 into Power Down Mode. Erase/Write cycles: • Flash memory – 100,000 minimum • ...
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... PSD813F1-A Figure 1. PSD813F1 Block Diagram 4 Preliminary ...
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... All PSD813F1 devices provide these features: 1 Mbit main Flash Memory, JTAG port, CPLD, DPLD, power management, and 27 I/O pins. The PSD813F1 also adds 64 bytes of PSD813F1 OTP memory for any use (product serial number, calibration constants, etc.). Once written, Family the OTP memory can never be altered ...
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... Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 1 Mbit Flash is the main memory of the PSD813F1 divided into eight equally-sized sectors that are individually selectable. The 256 Kbit EEPROM or Flash is divided into four equally-sized sectors. Each sector is individually selectable ...
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... Preliminary PSD813F1 5.4 I/O Ports Architectural The PSD813F1 has 27 I/O pins divided among four ports (Port and D). Each I/O pin can be individually configured for different functions. Ports and D can be Overview configured as standard MCU I/O ports, PLD I/O, or latched address outputs for (cont.) microcontrollers using multiplexed address/data busses. ...
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... The APD unit has a Power Down Mode that helps reduce power consumption. The PSD813F1 also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and the CPLD will latch its outputs and go to sleep until the next transition on its inputs ...
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... PSDsoft directly supports two low cost device programmers from ST, PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. The PSD813F1 is also supported by third party device programmers, see web site for current list. ...
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... PSD813F1-A 7.0 The following table describes the pin names and pin functions of the PSD813F1. Pins that have multiple names and/or functions are defined using PSD Configuration. Table 5. PSD813F1 Pin Name Pin Descriptions ADIO0-7 ADIO8-15 CNTL0 CNTL1 10 Pin* Type 30-37 I/O This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1 ...
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... PC1 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. CPLD Micro Cell (McellBC1) output. 3. Input to the PLDs. 4. TCK Input** for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PSD813F1-A Description 11 ...
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... PSD813F1-A Table 5. Pin Name Pin* Type PSD813F1 PC2 Pin Descriptions (cont.) PC3 PC4 PC5 PC6 12 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — write to or read from a standard output or input port. 2. CPLD Micro Cell (McellBC2) output. ...
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... CSI — chip select input. When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. 15, 38 Power pins 1,16,26 Ground pins Port A Port A (3:0) Port A (7:4) N/A Address [7:4] N/A N/A Address [3:0] Address [7:4] N/A N/A PSD813F1-A Description Port B Port B (3:0) Port B (7:4) Address [11:8] N/A Address [11:8] Address [15:12] Address [3:0] Address [7:4] Address [3:0] Address [7:4] 13 ...
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... PSD813F1-A 8.0 Table 7 shows the offset addresses to the PSD813F1 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the PSD813F1 internal PSD813F1 registers. Table 7 provides brief descriptions of the registers in CSIOP Register space. For a more detailed description, refer to section 9. ...
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... Preliminary 9.0 As shown in Figure 1, the PSD813F1 consists of six major types of functional blocks: The Memory Blocks PSD813F1 PLD Blocks Functional Bus Interface Blocks I/O Ports Power Management Unit JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. ...
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... The Ready/Busy Pin (PC3) Pin PC3 can be used to output the Ready/Busy status of the PSD813F1. The output on the pin will be a ‘0’ (Busy) when Flash or EEPROM memory blocks are being written to, or when the Flash memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase operation is in progress ...
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... ROM device). An invalid combination or time-out while addressing the EEPROM block will cause the offending byte to be interpreted as a single operation. The PSD813F1 supports these instructions (see Table 9): Flash memory: Erase memory by chip or sector ...
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... PSD813F1-A The Table 9. Instructions PSD813F1 Functional Blocks (cont.) Instruction Read Flash Identifier (Note 3, 5) Read OTP Row (Note 4) Read Sector Protection Status (Notes 3, 5) Program a Flash Byte (Note 5) Erase one Flash Sector (Note 5) Erase the whole Flash (Note 5) Suspend Sector Erase ...
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... Table 9). During the read operation, address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select signal (FSi) must be active. The Flash ID is E3h for the PSD813F1. The MCU can read the ID only when it is executing from the EEPROM. ...
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... EEPROM Return instruction must be executed (see Table 9). 9.1.1.5.5 Read the Erase/Program Status Bits The PSD813F1 provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of Flash memory. Bits are also available to show the status of writes to EEPROM. These status bits minimize the time that the microcontroller spends performing these tasks and are defined in Table 10 ...
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... No erasure will be performed. 9.1.1.5.7 Toggle Flag DQ6 The PSD813F1 offers another way for determining when the EEPROM write or the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or EESi is true, the DQ6 will toggle from ‘0’ to ‘1’ and ‘1’ to ‘0’ on subsequent attempts to read any byte of the memory ...
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... Write a Page to EEPROM Writing data to EEPROM using page mode is more efficient than writing one byte at a time. The PSD813F1 EEPROM has a 64 byte volatile buffer that the MCU may fill before an internal EEPROM storage operation is initiated. Page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. ...
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... EEPROM memory, with no more than 120 µsec between writes. The addresses 555h and AAAh are located on different pages of EEPROM. This is how the PSD813F1 distinguishes these instruction sequences from ordinary writes to EEPROM, which are expected to be within a single EEPROM page ...
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... Although erasing Flash memory occurs on a sector basis, programming Flash memory occurs on a byte basis. The PSD813F1 main Flash and optional boot Flash require the MCU to send an instruction to program a byte or perform an erase function (see Table 9). This differs from EEPROM, which can be programmed with simple MCU bus write operations (unless EEPROM SDP mode is enabled) ...
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... Functional Blocks When the MCU issues a programming instruction, the embedded algorithm within the PSD813F1 begins. The MCU then reads the location of the byte to be programmed in Flash (cont.) to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the original data byte to be programmed ...
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... When the MCU issues a programming instruction, the embedded algorithm within the (cont.) PSD813F1 begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling (two consecutive reads yield the same value), and the Error bit on DQ5 remains ‘ ...
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... If DQ3 is ‘0’, the Sector Erase instruction has been received and the timeout is counting. If DQ3 is ‘1’, the timeout has expired and the PSD813F1 is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode ...
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... PSD813F1-A The 9.1.1.8.4 Flash Erase Resume Instruction PSD813F1 If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any Functional address while an appropriate Chip Select (FSi) is true. (See Table 9.) Blocks (cont.) 9 ...
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... The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PC2). If you have an external battery connected to the PSD813F1, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains greater ...
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... C500 family, have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD813F1 can reside in either space or both spaces. This is controlled through manip- ulation of the VM register that resides in the PSD’s CSIOP space. ...
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... Figure 9. 80C31 Memory Mode – Combined Space Mode RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 FLASH DPLD RS0 EES0-3 FS0 PSEN RD DPLD RS0 EES0-3 FS0-7 PSD813F1-A EEPROM SRAM FLASH EEPROM SRAM OE 31 ...
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... PSD813F1-A The 9.1.4 Page Register PSD813F1 The eight bit Page Register increases the addressing capability of the microcontroller by a factor 256. The contents of the register can also be read by the microcontroller. The Functional outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be Blocks included in the Flash Memory, EEPROM, and SRAM chip select equations ...
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... NOTE: The address inputs are A[19:4] in 80C51XA mode. The Turbo Bit in PSD813F1 The PLDs in the PSD813F1 can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing ...
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... OUTPUT MICRO CELL FEEDBACK 16 CPLD 73 DIRECT MICRO CELL INPUT TO MCU DATA BUS INPUT MICRO CELL & INPUT PORTS 24 3 PORT D INPUTS 8 FLASH MEMORY SELECTS 4 EEPROM SELECTS 1 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL SELECTS 1 JTAG SELECT DIRECT MICRO CELL ACCESS FROM MCU DATA BUS ...
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... Four I/O ports. Each of the blocks are described in the subsections that follow. The Input and Output Micro Cells are connected to the PSD813F1 internal data bus and can be directly accessed by the microcontroller. This enables the MCU software to load data into the Output Micro Cells or read data from both the Input and Output Micro Cells. ...
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... CNTRL [ 2 READ/WRITE CONTROL SIGNALS) (3) (1) RESET (1) RD_BSY * NOTE: The address inputs are A[19:4] in 80C51XA mode. EES0 3 EES1 3 EEPROM SELECTS EES2 3 EES3 3 3 FS0 FLASH MEMORY SECTOR SELECTS FS7 RS0 2 SRAM SELECT CSIOP I/O DECODER SELECT PSEL0 PERIPHERAL I/O MODE SELECT PSEL1 JTAGSEL ...
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... Preliminary Figure 13. The Micro Cell and I/O Port BUS INPUT PLD MUX MUX ARRAY AND BUS INPUT PLD PSD813F1-A MUX MUX 37 ...
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... PSD813F1-A The 9.2.2.1 Output Micro PSD813F1 Eight of the Output Micro Cells are connected to Ports A and B pins and are named as McellAB0-7. The other eight Micro Cells are connected to Ports B and C pins and are Functional named as McellBC0- McellAB output is not assigned to a specific pin in PSDabel, Blocks the Micro Cell Allocator will assign it to either Port ...
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... PLD output in PSDsoft. If the OMC output is declared as an internal node and not as a Port pin output in the PSDabel file, then the Port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND array. PSD813F1-A 39 ...
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... PSD813F1-A The Figure 14. CPLD Output Micro Cell PSD813F1 Functional Blocks (cont.) 40 ARRAY AND BUS INPUT PLD Preliminary ...
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... The Slave can also write to the Port A IMCs and the Master can then read the IMCs directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs RD, WR, and Slave_CS. PSD813F1-A 41 ...
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INTERNAL DATA BUS CELL _ RD INPUT MICRO ENABLE ( .OE ) OUTPUT PT MICRO CELLS BC AND MICRO CELL AB PT MUX FEEDBACK Q G LATCH DIRECTION REGISTER PORT ...
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... PSD813F1 CPLD MCU- RD MCU- WR MASTER MCU D [ 7:0 ] MCU -RD SLAVE– SLAVE– READ PORT A DATA OUT REGISTER PORT A MCU-WR SLAVE–WR PORT A INPUT MICRO CELL Q D SLAVE MCU ...
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... Figure 18 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a PSD813F1. The address bus is connected to the ADIO Port, and the data bus is connected to Port A. Port tri-state mode when the PSD813F1 is not accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports may be used for additional address inputs ...
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... MICRO 7:0 ] CONTROLLER BHE ALE RESET PSD813F1 PORT A ( OPTIONAL ) ADIO PORT PORT B ( OPTIONAL ) WR ( CNTRL0 ) RD ( CNTRL1 ) BHE ( CNTRL2 ) PORT C RST ALE ( PD0 ) PORT D ...
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... D [ 7:0 ] MICRO- CONTROLLER BHE ALE RESET PSD813F1 D [ 7:0 ] PORT A ADIO PORT A [ 23:16 ] PORT B (OPTIONAL CNTRL0 ) RD ( CNTRL1 ) BHE ( CNTRL2 ) PORT RST C ALE ( PD0 ) PORT D ...
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... Figure 20. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD813F1. The A16 connection to the PA0 pin allows for a larger address input to the PSD813F1. Configuration 4 is shown in Figure 21. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2. ...
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... Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to ALE does not apply. 9.3.4.4 68HC11 Figure 23 shows an interface to a 68HC11 where the PSD813F1 is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR signals for external devices. ...
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... Figure 19. Interfacing the PSD813F1 with an 80C31 80C31 31 EA/ RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 P1.6 8 P1.7 RESET Figure 20. Interfacing the PSD813F1 to the 80C251, with One Read Input 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 A17 9 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 ...
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... PSD813F1-A Figure 21. Interfacing the PSD813F1 to the 80C251, with Read and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1 10 RESET RST 35 EA RESET Figure 22. Interfacing the PSD813F1 to the 80C51XA, 8-Bit Data Bus 80C51XA 21 XTAL1 20 XTAL2 11 RXD0 ...
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... Preliminary Figure 23. Interfacing the PSD813F1 with a 68HC11 68HC11 RESET RESET 19 IRQ 18 XIRQ 2 MODB 34 PA0 33 PA1 32 PA2 43 PE0 44 PE1 45 PE2 46 PE3 47 PE4 48 PE5 49 PE6 50 PE7 52 VRH 51 VRL AD0 AD1 AD2 AD3 31 PA3 AD4 30 PA4 AD5 29 PA5 AD6 28 PA6 AD7 27 PA7 ...
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... PSD813F1-A The 9.4 I/O Ports PSD813F1 There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing Functional multiple functions per port. The ports are configured using PSDsoft Configuration or by the Blocks microcontroller writing to on-chip registers in the CSIOP address space ...
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DATA OUT REG. DATA OUT ADDRESS ADDRESS D Q ALE G MICRO CELL OUTPUTS EXT CS READ MUX P D DATA IN B CONTROL REG DIR REG ENABLE PRODUCT TERM ( ...
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... PSD813F1-A The 9.4.2 Port Operating Modes PSD813F1 The I/O Ports have several modes of operation. Some modes can be defined using PSDabel, some by the microcontroller writing to the Control Registers in CSIOP space, and Functional some by both. The modes that can only be defined using PSDsoft must be programmed Blocks into the device and cannot be changed unless the device is reprogrammed ...
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... MCU I/O Mode In the MCU I/O Mode, the microcontroller uses the PSD813F1 ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD813F1 are mapped into the microcontroller address space. The addresses of the ports are listed in Table 7. A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the Control Register ...
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... PSD813F1-A The 9.4.2.3 Address Out Mode PSD813F1 For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external Functional devices. Either the output enable or the corresponding bits of both the Direction Register Blocks and Control Register must be set to a ‘ ...
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... Table 23, are used for setting the port configurations. The default power-up state for each register in Table 23 is 00h. Table 23. Port Configuration Registers Register Name Control Direction Drive Select* * NOTE: See Table 27 for Drive Register bit definition. PSEL DATA BUS Port MCU Access A,B Write/Read A,B,C,D Write/Read A,B,C,D Write/Read PSD813F1-A PA0 - PA7 57 ...
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... PSD813F1-A The 9.4.3.1 Control Register PSD813F1 Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode, and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B Functional have an associated Control Register. Blocks (cont ...
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... Drain Open Open Open Open Drain Drain Drain Drain Open Open Open Open Drain Drain Drain Drain PSD813F1-A Bit 3 Bit 2 Bit 1 Bit 0 Slew Slew Slew Slew Rate Rate Rate Rate Slew Slew Slew Slew Rate Rate Rate Rate Open ...
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... PSD813F1-A The 9.4.4 Port Data Registers PSD813F1 The Port Data Registers, shown in Table 28, are used by the microcontroller to write data to or read data from the ports. Table 28 shows the register name, the ports having each Functional register type, and microcontroller access for each register type. The registers are described Blocks below ...
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... Data Port – Port A to D[7:0] for 8 bit non-multiplexed bus Multiplexed Address/Data port for certain types of microcontroller interfaces. Peripheral Mode – Port A only McellBC[7:0] can be connected to Port B or Port C. – Via the input Micro Cells. pins PA[7:4] and PB[7:4] can be configured to Open Drain Mode. PSD813F1-A 61 ...
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DATA OUT REG ADDRESS ADDRESS 7 15:8 ] ALE G MICRO CELL OUTPUTS READ MUX CONTROL REG DIR REG ENABLE ...
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... Address In – Additional high address inputs using the Input Micro Cells. In-System Programming – JTAG port can be enabled for programming/erase of the PSD813F1 device. (See Section 9.6 for more information on JTAG programming.) Open Drain – Port C pins can be configured in Open Drain Mode Battery Backup features – PC2 can be configured as a Battery Input (Vstby) pin. ...
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... PSD813F1-A The Figure 27. Port C Structure PSD813F1 Functional Blocks (cont.) 64 BUS DATA INTERNAL Preliminary ...
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DATA OUT REG. DATA OUT ECS [ 2:0 ] READ MUX P D DATA IN B DIR REG PORT D PIN OUTPUT MUX OUTPUT SELECT ENABLE PRODUCT TERM (.OE) CPLD-INPUT ...
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ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 ...
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... Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. The PSD813F1 has a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current) ...
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... E clock to the CLKIN input (PD1). You should instead connect an independent clock signal to the CLKIN input. The clock frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD813F1 will keep going into Power Down Mode. 68 Ports ...
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... Set PMMR0 Bit OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 2 through 6. ALE/AS idle No for 15 CLKIN clocks? Yes PSD in Power Down Mode PSD813F1-A DISABLE BUS INTERFACE PD EEPROM SELECT FLASH SELECT PD PLD SRAM SELECT POWER DOWN ( PDN ) SELECT ...
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... PSD813F1-A The Table 31. Power Management Mode Registers (PMMR0, PMMR2)** PSD813F1 PMMR0 Functional Bit 7 Blocks * (cont.) *** Bits and 7 are not used, and should be set to 0. *** The PMMR0, and PMMR2 register bits are cleared to zero following power up. *** Subsequent reset pulses will not clear the registers. ...
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... Input Clock The PSD813F1 provides the option to turn off the CLKIN input to the PLD to save AC power consumption. The CLKIN is an input to the PLD AND array and the Output Micro Cells. During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be disconnected from the PLD AND array or the Micro Cells by setting bits “ ...
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... PSD813F1 remains in the reset state for an additional tOPR (minimum 120 ns) nanoseconds before the first memory access is allowed. The PSD813F1 Flash or EEPROM memory is reset to the read array mode upon power up. The FSi and EESi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possi- bility of a byte being written on the first edge of a write strobe signal ...
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... SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset. 9.6 Programming In-Circuit using the JTAG Interface The JTAG interface on the PSD813F1 can be enabled on Port C (see Table 34). All memory (Flash and EEPROM), PLD logic, and PSD configuration bits may be programmed through the JTAG interface ...
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... PSD813F1-A The 9.6.1 Standard JTAG Signals PSD813F1 The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are Functional inputs, waiting for a serial command from an external JTAG controller device (such as Blocks FlashLink or Automated Test Equipment) ...
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... TERR does not apply to EEPROM. TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD813F1 device is in read array mode (Flash memory and EEPROM contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to EEPROM. TSTAT and TERR can be configured as open-drain type signals during an “ ...
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... PSD813F1-A Absolute Symbol Maximum T STG Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent Operating Range Commercial Industrial Commercial Industrial Recommended Symbol Operating Conditions Parameter Storage Temperature PLDCC Commercial Operating Temperature Industrial Voltage on any Pin ...
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... In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD813F1 is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". The AC power component gives the PLD, EPROM, and SRAM mA/MHz specification. ...
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... PSD813F1-A AC/DC Figure 33a. PLD I Parameters (cont.) Example of PSD813F Typical Power Calculation at V Conditions Highest Composite PLD input frequency MCU ALE frequency (Freq ALE) Operational Modes Number of product terms used Turbo Mode Calculation (typical numbers used) I total = Ipwrdown x %pwrdown + %normal x CC This is the operating power with no EEPROM writes or Flash erases. Calculation is ...
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... Preliminary AC/DC Example of PSD813F1 Typical Power Calculation at V Parameters Conditions (cont.) Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report total product terms ...
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... PSD813F1-A PSD813F1 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V V Min for Flash Erase and Program ...
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CPLD Combinatorial Timing (5 V ± 10%) Symbol Parameter Conditions CPLD Input Pin/Feedback CPLD Combinatorial Output t CPLD Input to CPLD EA Output Enable t CPLD Input to CPLD ER Output Disable t CPLD Register Clear or ...
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CPLD Micro Cell Synchronous Clock Mode Timing Symbol Parameter Conditions Maximum Frequency 1/( External Feedback Maximum Frequency f Internal Feedback 1/( MAX CNT Maximum Frequency 1/( ...
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CPLD Micro Cell Asynchronous Clock Mode Timing Symbol Parameter Conditions Maximum Frequency 1/( External Feedback Maximum Frequency f Internal Feedback 1/( MAXA CNTA Maximum Frequency ...
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Input Micro Cell Timing (5 V ± 10% Versions) Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input Low Time NIB Input to Combinatorial Delay ...
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... B – Vstby Output M – Output Micro Cell Signal Behavior t – Time L – Logic Level Low or ALE H – Logic Level High V – Valid X – No Longer a Valid Logic Level Z – Float PW – Pulse Width t – Time from Address Valid to ALE Invalid. AVLX PSD813F1-A 85 ...
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... PSD813F1-A Microcontroller Interface – PSD813F1 AC/DC Parameters (5V ± 10% Versions) Read Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-Bit Bus ...
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... Preliminary Microcontroller Interface – PSD813F1 AC/DC Parameters (5V ± 10% Versions) Write, Erase and Program Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time ...
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... PSD813F1-A Microcontroller Interface – PSD813F1 AC/DC Parameters (5V ± 10% Versions) Port A Peripheral Data Mode Read Timing Symbol Parameter t Address Valid to Data AVQV (PA) Valid t CSI Valid to Data Valid SLQV (PA Data Valid t RLQV (PA Data Valid 8031 Mode t Data In to Data Out Valid DVQV (PA) ...
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... Preliminary Microcontroller Interface – PSD813F1 AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from t APD Enable to Internal CLWH PDN Valid Signal NOTE the CLKIN clock period. CLCL V Timing (5 V ± 10%) ...
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... PSD813F1-A Microcontroller Interface – PSD813F1 AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed) WHQV3 t Sector Erase (Not Preprogrammed) WHQV2 t Byte Program WHQV1 Program/Erase Cycles (Per Sector) ...
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... Preliminary PSD813F1V DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V V Min for Flash Erase and Program ...
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... PSD813F1-A PSD813F1V AC/DC Parameters – CPLD Timing Parameters (3 3.6 V Versions) CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/Feedback CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input to CPLD Output t ER Disable CPLD Register Clear or t ARP Preset Delay CPLD Register Clear or ...
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... Preliminary PSD813F1V AC/DC Parameters – CPLD Timing Parameters (3 3.6 V Versions) CPLD Micro Cell Asynchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAXA Internal Feedback ( f CNTA Maximum Frequency Pipelined Data t Input Setup Time SA t Input Hold Time HA t Clock High Time ...
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... PSD813F1-A Microcontroller AC Symbols for PLD Timing. Interface – Example: PSD813F1V AC/DC Signal Letters Parameters A – Address Input C – CEout Output (3 3 – Input Data Versions) E – E Input G – Internal WDOG_ON signal I – Interrupt Input L – ALE Input N – Reset Input or Output P – ...
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... Preliminary Microcontroller Interface – PSD813F1V AC/DC Parameters (3 3.6 V Versions) Read Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid (Notes 3 and 6) AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-Bit Bus ...
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... PSD813F1-A Microcontroller Interface – PSD813F1V AC/DC Parameters (3 3.6 V Versions) Write, Erase and Program Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time ...
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... Preliminary Microcontroller Interface – PSD813F1V AC/DC Parameters (3 3.6 V Versions) Port A Peripheral Data Mode Read Timing Symbol Parameter t Address Valid to Data Valid AVQV (PA) t CSI Valid to Data Valid SLQV (PA Data Valid t RLQV (PA Data Valid 8031 Mode t Data In to Data Out Valid ...
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... PSD813F1-A Microcontroller Interface – PSD813F1V AC/DC Parameters (3 3.6 V Versions) Power Down Timing (3 3.6 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to Internal PDN Valid Signal NOTE the CLKIN clock period. CLCL V Timing (3 3.6 V Versions) ...
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... Preliminary Microcontroller Interface – PSD813F1V AC/DC Parameters (3 3.6 V Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Program Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed) WHQV3 t Sector Erase (Not Preprogrammed) WHQV2 t Byte Program WHQV1 Program/Erase Cycles (Per Sector) ...
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... PSD813F1-A Figure 34. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS) E R/W t AVPV * t and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. AVLX LXAX 100 * t AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS t SLQV t THEH ADDRESS OUT ...
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... BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT PSD813F1-A DATA VALID DATA VALID t DVWH t WHDX t WHAX t EHEL t ELTL t WLMV t WHPV STANDARD MCU I/O OUT 101 ...
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... PSD813F1-A Figure 36. Peripheral I/O Read Timing ALE/AS A/D BUS CSI RD Figure 37. Peripheral I/O Write Timing ALE/ BUS WR 102 ADDRESS t AVQV ( PA) t SLQV ( PA) t RLQV ( PA) t RLRH ( PA) ADDRESS tWLQV DATA VALID t QXRH ( PA) t RHQZ ( PA) t DVQV ( PA) DATA ON PORT A DATA OUT tWHQZ (PA) (PA) tDVQV (PA) ...
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... Preliminary Figure 38. Combinatorial Timing – PLD CPLD INPUT CPLD OUTPUT Figure 39. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT PSD813F1-A 103 ...
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... PSD813F1-A Figure 40. Asynchronous Clock Mode Timing (Product-Term Clock) CLOCK INPUT REGISTERED OUTPUT Figure 41. Input Micro Cell Timing (Product-Term Clock) PT CLOCK INPUT OUTPUT 104 tCHA tCLA tSA tHA t t INH INL t IS Preliminary tCOA INO ...
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... Preliminary Figure 42. Input to Output Disable/Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Figure 43. Asynchronous Reset/ Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 44. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO tER tARPW tARP t ISCCH t ISCCL t t ISCPSU ISCPH PSD813F1-A tEA t ISCPZV t ISCPCO t ISCPVZ 105 ...
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... PSD813F1-A Figure 45. Reset Timing OPERATING LEVEL V CC RESET Figure 46. Key to Switching Waveforms WAVEFORMS 106 t NLNH– OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM DON'T CARE OUTPUTS ONLY Preliminary t NLNH t OPR WARM RESET OUTPUTS ...
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... Parameter Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for CNTL2 25°C and nominal supply voltages. A 3.0V TEST POINT 0V 2.01 V DEVICE UNDER TEST PSD813F1-A 2 Conditions Typical Max Unit OUT ...
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... PSD813F1-A PSD813F1-A 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) Pin Pin No. Assignments 108 Pin Assignments Pin No. GND 27 PB5 28 PB4 29 PB3 30 PB2 31 PB1 32 PB0 33 PD2 34 PD1 35 PD0 36 PC7 ...
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... PA7 40 PA6 41 PA5 42 PA4 43 PA3 44 GND 45 PA2 46 PA1 47 PA0 48 AD0 49 AD1 50 AD2 51 AD3 52 PSD813F1-A Pin Assignments AD4 AD5 AD6 AD7 VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1 PB7 PB6 GND PB5 PB4 PB3 PB2 PB1 ...
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... PSD813F1-A PSD813F1-A Figure 49. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC) Package Information Figure 50. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) 110 (Package Type PD2 PD1 9 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 (VSTBY) ...
Page 115
... View A .045 C View Inches Min Max 0.165 0.180 0.100 0.110 0.144 0.152 0.013 0.021 0.026 0.032 0.0097 0.0103 0.785 0.795 0.750 0.754 0.690 0.730 0.600 Reference 0.785 0.795 0.750 0.754 0.690 0.730 0.600 Reference 0.050 Reference 52 PSD813F1-A Notes 111 ...
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... PSD813F1-A Figure 50A. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type Index 3 Mark B Family: Plastic Quad Flatpack (PQFP) Symbol Min 0° A – A2 1. 12.95 D1 9.90 D3 7.80 E 12.95 E1 9.90 E3 7.80 e1 0. 112 Millimeters Max Notes 7° 2.35 2.10 0.38 Reference 0.23 13.45 10.10 Reference 13 ...
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... Selector Guide – PSD813F1-A Part # MCU PLDs/Decoders PSD PSD Data Path PLD Inputs @ @ Interface Input Micro Cells Output Micro Cells PLD Outputs PSD813F1 PSD813F1V 8 PLUS1 PSD813F2 PSD813F2V 8 PLUS1 PSD813F3 PSD813F3V 8 PLUS1 PSD813F4 PSD813F4V ...
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... PSD813F1-A Part Number Construction PSD Ordering Information Part Number PSD813F1-A-90J PSD813F1-A-90JI PSD813F1-A-90M PSD813F1-A-90MI PSD813F1-A-12JI PSD813F1-A-12MI PSD813F1-A-V-15J PSD813F1-A-V-15M PSD813F1-A-V-20JI PSD813F1-A-V-20MI 114 I 413A2 V -A -20 J Speed (ns) Package Type 90 52 Pin PLDCC 90 52 Pin PLDCC ...
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... PSD813F1-A REVISION HISTORY Table 1. Document Revision History Date Rev. Aug-2000 1.0 Document written in the WSI format Front page, and back two pages format, added to the PDF file 04-Jan-2002 1.1 References to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft Express ...
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... STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved www.st.com PSD813F1-A 3/3 ...