PSD813F1 STMICROELECTRONICS [STMicroelectronics], PSD813F1 Datasheet - Page 65

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PSD813F1

Manufacturer Part Number
PSD813F1
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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Preliminary
The
PSD813F1
Functional
Blocks
(cont.)
9.4.5 Ports A and B – Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 26. The two ports
can be configured to perform one or more of the following functions:
MCU I/O Mode
CPLD Output – Micro Cells McellAB[7:0] can be connected to Port A or Port B.
CPLD Input
Latched Address output – Provide latched address output per Table 30.
Address In – Additional high address inputs using the Input Micro Cells.
Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to fast slew rate,
Data Port – Port A to D[7:0] for 8 bit non-multiplexed bus
Multiplexed Address/Data port for certain types of microcontroller interfaces.
Peripheral Mode – Port A only
– Via the input Micro Cells.
McellBC[7:0] can be connected to Port B or Port C.
pins PA[7:4] and PB[7:4] can be configured to Open Drain
Mode.
PSD813F1-A
61

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