CY6264-55SNXCT Cypress Semiconductor Corp, CY6264-55SNXCT Datasheet

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CY6264-55SNXCT

Manufacturer Part Number
CY6264-55SNXCT
Description
IC SRAM 64KBIT 55NS 28SOIC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY6264-55SNXCT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
64K (8K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. **
Features
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
and three-state drivers. Both devices have an automatic
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
features
CE
CE
WE
OE
1
2
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
2
), and active LOW output enable (OE)
COLUMN DECODER
INPUT BUFFER
256 x 32 x 8
ARRA Y
1
, CE
2
, and OE
1
3901 North First Street
POWER
DOWN
), an active
power-down feature (CE
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
inputs are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
0
through A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
San Jose
2
active HIGH, while WE remains inactive or
12
). Reading the device is accomplished by
0
through I/O
,
1
8K x 8 Static RAM
), reducing the power consumption
CA 95134
Pin Configuration
2
GND
is HIGH, data on the eight data
I/O
I/O
I/O
A
A
A
NC
A
A
A
A
A
A
10
11
12
4
5
6
7
8
9
0
1
2
7
) is written into the memory
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
Revised June 27, 2005
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
408-943-2600
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
3
2
1
0
2
1
7
6
5
4
3
CY6264
1
1
and WE
and OE
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Related parts for CY6264-55SNXCT

CY6264-55SNXCT Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 001-02367 Rev. ** power-down feature (CE by over 70% when deselected. The CY6264 is packaged in a 450-mil (300-mil body) SOIC. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE , and OE 2 inputs are both LOW and CE input/output pins (I/O ...

Page 2

... Max., = GND = Max., Com’ Ind’ > V Com’ IH, Ind’ > V – 0.3V, Com’ > V – 0. < 0. Ind’l CY6264 CY6264-70 Unit 70 ns 100 mA 200 20/ Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° – +85 C 6264-55 6264-70 Max ...

Page 3

... Tested initially and after any design or process changes that may affect these parameters. Document #: 001-02367 Rev. ** [3] 6264-55 Min Test Conditions T = 25° MHz 5. less than t for any given device. HZCE LZCE LOW, CE HIGH, and WE LOW. Both signals must be LOW to initiate a write and either 1 2 CY6264 6264-70 Max. Min. Max. Unit ...

Page 4

... WE is HIGH for read cycle. 11. Data I/O is High Document #: 001-02367 Rev 481Ω 3. GND 255Ω JIG AND SCOPE (b) 1.73V OHA DOE DATA VALID 50 IH CY6264 ALL INPUT PULSES 90% 90% 10% 10% < < DATA VALID t HZOE t HZCE HIGH IMPEDANCE t PD 50% Page ICC ISB [+] Feedback ...

Page 5

... DATA UNDEFINED Note: 12 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 001-02367 Rev SCE1 t SCE2 PWE t SD DATA VALID IN t HZWE HIGH IMPEDANCE SCE1 SCE2 PWE t SD DATA VALID IN t HZWE CY6264 LZWE HIGH IMPEDANCE Page [+] Feedback ...

Page 6

... TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. =25°C A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) CY6264 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. =25° 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...

Page 7

... Truth Table Address Designators Address Name A10 A11 A12 Document #: 001-02367 Rev Input/Output X High Z Deselect/Power-Down X High Z Deselect L Data Out Read X Data In Write H High Z Deselect Address Function CY6264 Mode Pin Number Page [+] Feedback ...

Page 8

... Ordering Code 55 CY6264-55SC 70 CY6264-70SC 55 CY6264-55SNC 55 CY6264-55SNXC 70 CY6264-70SNC 70 CY6264-70SNXC 70 CY6264-70SNI 70 CY6264-70SNXI Shaded areas contain advance information. Package Diagrams 28-lead (300 mil) SNC Package Outline (Narrow Body) SN28 0.702 0.710 Note: 13. Not recommended for new designs. A 0.050 TYP. Document #: 001-02367 Rev. ** Package ...

Page 9

... SOIC with Wide Body S28.33 PIN 1 ID DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 0.79gms 0.460[11.684] 0.480[12.192] 0.338[8.585] 0.346[8.788] SEATING PLANE 0.094[2.387] 0.110[2.794] 0.004[0.102] 0.002[0.050] 0.014[0.355] CY6264 MIN. MAX. PART # S28.33 STANDARD PKG. SZ28.33 LEAD FREE PKG. 0.008[0.203] 0.030[0.762] 0.012[0.304] 0.050[1.270] 51-85058-*B Page [+] Feedback ...

Page 10

... Document History Page Document Title:CY6264 Static RAM Document Number: 001-02367 Orig. of REV. ECN NO. Issue Date Change ** 384870 See ECN Document #: 001-02367 Rev. ** Description of Change PCI Spec # change from 38-00425 to 001-02367 CY6264 Page [+] Feedback ...

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