M25P64-VMF6P NUMONYX, M25P64-VMF6P Datasheet - Page 16

no-image

M25P64-VMF6P

Manufacturer Part Number
M25P64-VMF6P
Description
IC FLASH 64MBIT 50MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheets

Specifications of M25P64-VMF6P

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8M x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Memory Configuration
8M X 8
Ic Interface Type
Serial, SPI
Clock Frequency
75MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P64-VMF6P
Manufacturer:
ST
Quantity:
7 093
Part Number:
M25P64-VMF6P
Manufacturer:
ST
0
Part Number:
M25P64-VMF6P
Manufacturer:
ST
Quantity:
20 000
Part Number:
M25P64-VMF6P,M25P64-VMF6TP
Manufacturer:
ADI
Quantity:
379
Part Number:
M25P64-VMF6P-6JBS
Manufacturer:
RENESAS
Quantity:
1 350
Part Number:
M25P64-VMF6P-6JBS
Manufacturer:
ST
0
Part Number:
M25P64-VMF6P/XDY7S6JBS99-6E
Manufacturer:
ST
0
Part Number:
M25P64-VMF6PG
Manufacturer:
ST
0
4.8
16/55
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 6.
HOLD
C
Hold condition activation
Figure
6).
(standard use)
Condition
Hold
Figure
(non-standard use)
6).
Condition
Hold
AI02029D

Related parts for M25P64-VMF6P