CY7C1565V18-400BZI Cypress Semiconductor Corp, CY7C1565V18-400BZI Datasheet - Page 10

• Manufacturer Part Number: CY7C1565V18-400BZI
• Description: IC SRAM 72MBIT 400MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1565V18-400BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The truth table for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follows.
Truth Table
The write cycle description table for CY7C1561V18 and CY7C1563V18 follows.
Write Cycle Descriptions
Notes
Document Number: 001-05384 Rev. *F
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
Read Cycle:
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and a
half cycles; read data on
two consecutive K and K
rising edges.
NOP: No Operation
Standby: Clock Stopped
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges also.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
11. Is based on a write cycle was initiated per the
BWS
NWS
H
H
H
H
second read or write request.
BWS
L
L
L
L
0
0
/
2
Operation
, and BWS
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
3
can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
L–H
L–H
L–H
L–H
K
–
–
–
–
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence:
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence:
K
–
–
–
–
L-H
L-H
L-H
Stopped X
During the data portion of a write sequence:
CY7C1561V18 − both nibbles (D
CY7C1563V18 − both bytes (D
CY7C1561V18 − both nibbles (D
CY7C1563V18 − both bytes (D
During the data portion of a write sequence:
CY7C1561V18 − only the lower nibble (D
CY7C1563V18 − only the lower byte (D
CY7C1561V18 − only the lower nibble (D
CY7C1563V18 − only the lower byte (D
During the data portion of a write sequence:
CY7C1561V18 − only the upper nibble (D
CY7C1563V18 − only the upper byte (D
CY7C1561V18 − only the upper nibble (D
CY7C1563V18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
K
H
L
H
RPS WPS
The write cycle description table for CY7C1561V18 and CY7C1563V18 follows.
[10]
[9]
↑
L
X
H
X
represents rising edge.
[10]
D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Q(A) at K(t + 2)↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4) ↑
D = X
Q = High-Z
Previous State
DQ
[17:0]
[17:0]
[7:0]
[7:0]
) are written into the device.
) are written into the device.
) are written into the device,
) are written into the device,
D = X
Q = High-Z
Previous State
[8:0]
[8:0]
[17:9]
[17:9]
[3:0]
[3:0]
[7:4]
[7:4]
) is written into the device, D
) is written into the device, D
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
DQ
[3, 11]
CY7C1561V18, CY7C1576V18
CY7C1563V18, CY7C1565V18
D = X
Q = High-Z
Previous State
[3, 4, 5, 6, 7, 8]
DQ
[3, 11]
[17:9]
[17:9]
[8:0]
[8:0]
table. NWS
[7:4]
[7:4]
[3:0]
[3:0]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D = X
Q = High-Z
Previous State
0
, NWS
Page 10 of 28
1
DQ
, BWS
0
, BWS
1
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