MD8331-D2G-V18-X-P/Y SanDisk, MD8331-D2G-V18-X-P/Y Datasheet - Page 20

• Manufacturer Part Number: MD8331-D2G-V18-X-P/Y
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V18-X-P/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MD8831-D2G-V18-X-P/Y; MD8831-D2G-V18-X-P/Y; MD8832-D2G-V18-X-P/Y; MD8832-D2G-V18-X-P/Y

3.2
3.2.1
The system interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-
like) interface to DiskOnChip G4 enabling it to interface with various CPU interfaces, such as a
local bus, ISA bus, NOR interface, SRAM interface, EEPROM interface or any other compatible
interface. In addition, the EEPROM-like interface enables direct access to the Programmable Boot
Block to permit XIP (Execute-In-Place) functionality during system initialization.
A 13-bit wide address bus enables access to the DiskOnChip G4 8KB memory window (as shown
in Section 6.5).
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a
read cycle occurs while both the CE# and OE# inputs are asserted. Note that DiskOnChip G4 does
not require a clock signal. It features a unique analog static design, optimized for minimal power
consumption. The CE#, WE# and OE# signals trigger the controller (e.g., system interface block,
bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase,
delay the CPU resources. The signal is also asserted when a Data Protection violation has occurred.
This signal frees the CPU to run other tasks, continuing read/write operations with DiskOnChip G4
only after the IRQ# signal has been asserted and an interrupt handling routine (implemented in the
OS) has been called to return control to the TrueFFS driver.
The DMARQ# output is used to control multi-page DMA operations, and the CLK input is used to
support MultiBurst operation when reading flash data. See Section 4.1 for further information.
3.2.2
In this configuration, the address and data signals are multiplexed. The ID[1] input is driven by the
host AVD# signal, and the D[15:0] pins/balls, used for both address inputs and data, are connected
to the host AD[15:0] bus. While AVD# is asserted, the host drives AD[11:0] with bits [12:1] of the
address. Host signals AD[15:12] are not significant during this part of the cycle.
This interface is automatically used when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before the first read or write cycle to the controller. When using a
multiplexed interface, the value of ID[1] is internally forced to logic-0. The only possible device ID
values are 0 and 1; therefore, only up to two DiskOnChip G4 128MB (1Gb) devices may be
cascaded in multiplexed configuration (dual-die DiskOnChip G4 256MB (2Gb) cannot be cascaded
when used in a multiplexed interface).
3.3
The Configuration Interface block enables the designer to configure DiskOnChip G4 to operate in
different modes. The ID[1:0] signals are used in a cascaded configuration (refer to Section 9.6), the
DPD signal is used to enter and exit Deep Power-Down mode (see Section 6.3), the LOCK# signal
20
System Interface
Standard (NOR-Like) Interface
Multiplexed Interface
Configuration Interface
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00