MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet

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MD5811-D256-V3Q18-P

Manufacturer Part Number
MD5811-D256-V3Q18-P
Description
IC MDOC P3 256MB 48-TSOP
Manufacturer
SanDisk
Datasheet

Specifications of MD5811-D256-V3Q18-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
256M (32M x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
MD5811-D256-V3Q18-P
Manufacturer:
M-SYSTEM
Quantity:
860
Part Number:
MD5811-D256-V3Q18-P/Y
Manufacturer:
PULSE
Quantity:
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Highlights
Mobile DiskOnChip™ P3, a member of
M-Systems’ DiskOnChip™ family of
optimized memory solutions for new-generation
mobile handsets, provides high performance
and reliability using NAND flash technology. It
combines Toshiba’s cutting-edge 0.13 micron
NAND flash manufacturing process enhanced
for performance and reliability with
M-Systems’ x2 technology.
Mobile DiskOnChip P3 optimizes real estate
and cost structure by incorporating the flash
array and an embedded thin controller in a
single die. A boot block can be used to boot the
OS or initialize the CPU/platform, replacing
expensive NOR flash and further reducing
memory system costs.
Mobile DiskOnChip P3 provides:
1
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3V Core
Hardware protection and security-enabling
features
High capacity: 256Mbit (32MByte)
Device cascading option: up to 1Gbit
(128MByte)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Small form factors:
48-pin TSOP-I package
85-ball FBGA 7x10x1.2 mm package
Mobile DiskOnChip P3
M-Systems’ x2 Technology
256Mb Flash Disk with
Preliminary Data Sheet, Rev. 0.3
Enhanced performance with:
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC)
Maximized flash endurance with TrueFFS
6.1 (and higher) flash management software
Support for major mobile OSs, including:
Symbian OS, Pocket PC 2002/3,
Smartphone 2002/3, Palm OS, Nucleus,
Linux, Windows CE
Compatible with major mobile CPUs,
including TI OMAP, XScale, Motorola
DragonBall MX1 and Qualcomm
MSMxxxx.
Multi-plane operation
DMA support
MultiBurst operation
Turbo operation
Preliminary Data Sheet, June 2003
93-SR-009-8L
®

Related parts for MD5811-D256-V3Q18-P

MD5811-D256-V3Q18-P Summary of contents

Page 1

... M-Systems’ x2 Technology Highlights Mobile DiskOnChip™ P3, a member of M-Systems’ DiskOnChip™ family of optimized memory solutions for new-generation mobile handsets, provides high performance and reliability using NAND flash technology. It combines Toshiba’s cutting-edge 0.13 micron NAND flash manufacturing process enhanced for performance and reliability with M-Systems’ ...

Page 2

Performance MultiBurst read: 80 MB/sec Sustained read: 5 MB/sec Sustained write: 2.5 MB/sec Access time: Normal: 55 nsec Turbo: 33 nsec MultiBurst: 25 nsec Protection & Security-Enabling Features 16-byte Unique Identification (UID) number 6KByte user-controlled One Time Programmable (OTP) area ...

Page 3

TrueFFS Software Full hard-disk read/write emulation for transparent file system management Patented TrueFFS Flash file system management Automatic block management Data management to maximize the limit of typical flash life expectancy Dynamic virtual mapping Dynamic and static wear-leveling Programming, ...

Page 4

T C ABLE OF ONTENTS 1. Introduction ............................................................................................................................... 5 2. Product Overview ...................................................................................................................... 6 2.1 Product Description ............................................................................................................ 6 2.2 Standard Interface .............................................................................................................. 7 2.2.1 Pin/Ball Diagrams................................................................................................................. 7 2.2.2 System Interface .................................................................................................................. 9 2.2.3 Signal Description .............................................................................................................. 10 2.3 Multiplexed ...

Page 5

... Wear-Leveling .................................................................................................................... 39 7.1.6 Power Failure Management ............................................................................................... 40 7.1.7 Error Detection/Correction.................................................................................................. 40 7.1.8 Special Features Through I/O Control (IOCTL) Mechanism.............................................. 41 7.1.9 Compatibility ....................................................................................................................... 41 7.2 8KB Memory Window ....................................................................................................... 41 8. Register Descriptions ............................................................................................................. 42 8.1 Definition of Terms ........................................................................................................... 42 8.2 Reset Values .................................................................................................................... 42 8.3 No Operation (NOP) Register........................................................................................... 43 8.4 Chip Identification (ID) Register [0:1]................................................................................ 43 8.5 Test Register ...

Page 6

DMA Control Register [1:0]............................................................................................... 52 8.16 MultiBurst Mode Control Register..................................................................................... 54 9. Booting from Mobile DiskOnChip P3..................................................................................... 55 9.1 Introduction....................................................................................................................... 55 9.2 Boot Procedure in PC-Compatible Platforms ................................................................... 55 9.3 Boot Replacement ............................................................................................................ 56 9.3.1 PC Architectures ................................................................................................................ 56 ...

Page 7

DC Electrical Characteristics Over Operating Range ........................................................ 69 11.2.4 AC Operating Conditions.................................................................................................... 70 11.3 Timing Specifications........................................................................................................ 71 11.3.1 Read Cycle Timing Standard Interface .............................................................................. 71 11.3.2 Write Cycle Timing Standard Interface .............................................................................. 73 11.3.3 Read Cycle Timing Multiplexed Interface........................................................................... ...

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... Section 4: Major features and benefits of x2 technology Section 5: Detailed description of hardware protection and security-enabling features Section 6: Modes of operation Section 7: TrueFFS technology, including power failure management and 8KByte memory window Section 8: Register descriptions Section 9: Booting from Mobile DiskOnChip P3 Section 10: Hardware and software design considerations ...

Page 9

... Product Description Mobile DiskOnChip P3, packed in the smallest available FBGA package with 256Mb (32MB) capacity single-die device with an embedded thin flash controller and flash memory. It uses Toshiba’s cutting-edge, 0.13 micron NAND-based flash manufacturing process, enhanced by M-Systems’ proprietary x2 technology. M-Systems’ x2 technology provides performance enhancement with multi-plane operation, DMA support, turbo operation and MultiBurst operation ...

Page 10

Standard Interface 2.2.1 Pin/Ball Diagrams See Figure 1 and Figure 2 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the standard interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not be ...

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FBGA Package A0/ G VSS DPD H CE# OE# J RSRVD ...

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System Interface See Figure 3 for a simplified I/O diagram for a standard interface of Mobile DiskOnChip P3 256Mb. CE#, OC#, WE# A[12:0] D]15:0] System Interface Figure 3: Standard Interface Simplified I/O Diagram (Mobile DiskOnChip P3 256Mb) 9 Mobile ...

Page 13

... ST Output Enable, active low Configuration ST Identification. Configuration control to support up to four chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single-chip configuration Chip 2 = ID1, ID0 = VSS, VCCQ (0,1) Chip 3 = ID1, ID0 = VCCQ, VSS (1,0) Chip 4 = ID1, ID0 = VCCQ, VCCQ (1,1) ST Lock, active low ...

Page 14

Signal Pin No. DMARQ# 21 IRQ# 47 DPD 19 VCC 12 VCCQ 37 VSS 13, 25, 36, 48 RSRVD 20 The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...

Page 15

... Output Enable, active low Configuration ST Identification. Configuration control to support up to four chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single chip configuration Chip 2 = ID1, ID0 = VSS, VCCQ (0,1) Chip 3 = ID1, ID0 = VCCQ, VSS (1,0) ...

Page 16

Signal Ball No. IRQ# F8 DPD G1 VCC J4 VCCQ J5 VSS G2, J8 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open drain output, ...

Page 17

Multiplexed Interface 2.3.1 Pin/Ball Diagram See Figure 4 and Figure 5 for the Mobile DiskOnChip P3 256Mb pinout/ballout for the multiplexed interface. To ensure proper device functionality, pins/balls marked RSRVD are reserved for future use and should not be ...

Page 18

FBGA Package VSS D VSS VSS E VSS VSS F VSS VSS G DPD VSS H CE# OE# J RSRVD AD0 K AD8 ...

Page 19

System Interface See Figure 6 for a simplified I/O diagram. CE#, OE#, WE# Host System Bus System Interface Figure 6: Multiplexed Interface Simplified I/O Diagram 16 Mobile DiskOnChip P3 AD[15:0] ID0 LOCK# AVD# Configuration Data Sheet, Rev. 0.3 Mobile ...

Page 20

... DPD 19 ST Deep Power-Down. Used to enter and exit Deep Power-Down 17 Description System Interface Configuration cascaded in the same memory window. Chip 1 = ID0 = VSS; must be used for single-chip configuration Chip 2 = ID0 = VCCQ protection of selected partitions. Control initializing and should not be accessed KΩ pull-up resistor is required if this pin drives an input. ...

Page 21

Input Signal Pin No. Type VCCQ 37,22 - VCC 12 - VSS 5-11, 14-18, - 13, 25, 36, 48 RSRVD 20 - The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger input Open ...

Page 22

... G1 ST Deep Power-Down. Used to enter and exit Deep Power- 19 Description System Interface Configuration cascaded in the same memory window. Chip 1 = ID0 = VSS; must be used for single-chip configuration Chip 2 = ID0 = VCC protection of selected partitions. Control initializing and should not be accessed A 10 KΩ pull-up resistor is required if this ball drives an input KΩ ...

Page 23

Input Signal Ball No. Type VCC J4 - VCCQ J5 VSS G2,J8, - D7,C7,F6,E6, C6,C2,D2,E2 ,F2,D1,E1,F1 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input Schmidt Trigger ...

Page 24

T O HEORY OF PERATION 3.1 Overview Mobile DiskOnChip P3 consists of the following major functional blocks, as shown in Figure 7. *ADDR[0] and DPD are multiplexed on the same ball/pin. Figure 7: Mobile DiskOnChip P3 Simplified Block Diagram, ...

Page 25

... Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A 13-bit wide address bus enables access to the Mobile DiskOnChip 8KB memory window (as shown in Section 7.2). A 16-bit internal data bus is supported by parallel access to two 128Mb flash planes (for 256Mb single-die devices), each of which enables 8-bit access. This 16-bit data bus permits 16-bit wide access to the host ...

Page 26

... Mobile DiskOnChip P3. 3.4.1 Read/Write Protection Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or two independently programmable areas of the flash memory as read protected, write protected, or read/write protected. A protected partition may be protected by either/both of these hardware mechanisms: • ...

Page 27

One-Time Programmable (OTP) Area The 6KB OTP area is user programmable for complete customization. The user can write to this area once, after which it is automatically and permanently locked. After it is locked, the OTP area becomes read ...

Page 28

Download Engine (DE) Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the booting process. The download process is ...

Page 29

Flash Architecture Mobile DiskOnChip P3 256Mb consists of two 128Mb flash planes that consist of 1024 blocks each, divided in groups of 32 pages, as follows: • Page – Each page contains 512 bytes of user data and a ...

Page 30

Good Unit Good Unit Good Unit Bad Unit ~ ~ Good Unit Good Unit Good Unit Flash Plane 1 27 Internal Bus Aligned Unit Aligned Unit Aligned Unit ~ ~ ~ ~ Aligned Unit Aligned Unit Figure 10: Unaligned Multi-Plane ...

Page 31

T X ECHNOLOGY Mobile DiskOnChip P3 enhances performance using various proprietary techniques: • Parallel access to the separate 128Mb flash planes, thereby providing an internal 32-bit data bus. See Section 3.10 for further information. • MultiBurst operation to ...

Page 32

Host Internal data transfers /Flash_OE Data transfer from Flash Planes to FIFO External data transfers /DiskOnChip_OE Data transfer from FIFO to Host Note: Mobile DiskOnChip P3 does not support MultiBurst write operations. MultiBurst operation is controlled by 5 ...

Page 33

The LATENCY bit is the third bit that must be set in the MultiBurst Mode Control register. When the LATENCY bit is set to 0, the host can latch the first 16-bit data word two clock cycles after CLK0. This ...

Page 34

Set the bits in the Interrupt Control register (see Section 8) to enable interrupts on an ECC error and at the end of the DMA operation. 3. Write to the DMA Control register[0] to set the DMA_EN bit, the ...

Page 35

H P ARDWARE ROTECTION 5.1 Method of Operation Mobile DiskOnChip P3 enables the user to define two partitions that are protected (in hardware) against any combination of read or write operations. The two protected areas can be configured as ...

Page 36

Low-Level Structure of the Protected Area The first five blocks in Mobile DiskOnChip P3 contain foundry information, the Data Protect structures, IPL code, and bad block mapping information. See Figure 12. Bad Block Table and Factory-Programmed UID Data Protect ...

Page 37

Block 3 and 4 o Data Protect Structure 1. This structure contains configuration information on one of the two user-defined protected partitions. o IPL Code (2KB). This is the boot code that is downloaded by the DE to the internal ...

Page 38

M O ODES OF PERATION Mobile DiskOnChip P3 operates in one of three basic modes: • Normal mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading the DiskOnChip ...

Page 39

... Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register. The boot detector circuit triggers the software to set the device to Normal mode ...

Page 40

Applications that use Mobile DiskOnChip boot device must ensure that the device is not in Deep Power-Down mode before reading the Boot vector/instructions. This can be done by pulsing RSTIN# to the asserted state and waiting for ...

Page 41

... ECHNOLOGY 7.1 General Description M-Systems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition, since it operates under the OS file system layer (see Figure 14 completely transparent to the application ...

Page 42

... Wear-Leveling Flash memory can be erased a limited number of times. This number is called the erase cycle limit, or write endurance limit, and is defined by the flash array vendor. The erase cycle limit applies to each individual erase block in the flash device. In Mobile DiskOnChip P3, the erase cycle limit of the flash is 100,000 erase cycles ...

Page 43

... If wear-leveling were only applied on newly written pages, static areas would never be cycled. This limited application of wear-leveling would lower life expectancy significantly in cases where flash memory contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media ...

Page 44

... The 2KB Programmable Boot Block is in section 0 and section 3, to support systems that search for a checksum at the boot stage both from the top and bottom of memory. The addresses described here are relative to the absolute starting address of the 8KB memory window. ...

Page 45

R D EGISTER ESCRIPTIONS This section describes various Mobile DiskOnChip P3 registers and their functions, as listed in Table 5. Most Mobile DiskOnChip P3 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 103E 1000/1074 1004 1006 1008 ...

Page 46

... Chip Identification Register[1]: FDFFH 8.5 Test Register Description: This register enables software to identify multiple Mobile DiskOnChip P3 devices or multiple aliases in the CPUs memory space. Data written is stored but does not affect the behavior of Mobile DiskOnChip P3. Address (hex): 1004 Type: Read/Write Reset Value: 0 Bit No ...

Page 47

Bus Lock Register Description: This register provides a mechanism for a CPU to request and hold sole access rights to Mobile DiskOnChip P3 in multiprocessor applications. The following algorithm must be implemented to ensure that only one CPU at ...

Page 48

Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...

Page 49

... DiskOnChip Control register, the complement of that data byte must also be written to the Control Confirmation register. The two writes cycles must not be separated by any other read or write cycles to the Mobile DiskOnChip P3 memory space, except for reads from the Programmable Boot Block space. Address (hex): 100C/1072 Bit 7 ...

Page 50

Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bits ID[0:1] is compared to the value of the ID configuration input pins/balls. The device whose ID input ...

Page 51

Interrupt Control Register Description: This 16-bit register controls how interrupts are generated by Mobile DiskOnChip P3, and indicates which of the following five sources has asserted an interrupt: 0: Flash array is ready 1: Data protection violation 2: Reading ...

Page 52

Bit No. 14 EDGE. Selects edge or level triggered interrupts: 0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt is cleared. 1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low and return to ...

Page 53

Output Control Register Description: This register controls the behavior of certain output signals. This register is reset by a hardware reset, not by entering Reset mode. Note: When multiple devices are cascaded, writing to this register will affect all ...

Page 54

DPD Control Register Description: This register specifies the behavior of the DPD input signal. Address (hex): 107C Bit 7 Bit 6 Read/Write Description PD_OK Reset Value 0 Bit No. 3-0 MODE[0:3]. Controls the behavior of the DPD input: 0000: ...

Page 55

DMA Control Register [1:0] Description: These two 16-bit registers specify the behavior of the DMA operation. Address (hex): 1078/107A Bit 7 Bit 6 Read/Write R Description RFU_0 Reset Value 0 Bit 15 Bit 14 Read/Write R Description DMA_EN PAUSE ...

Page 56

Read/Write Description Reset Value 0 Bit No. 9-0 NEGATE_COUNT. When the EDGE bit of DMA Control register[ this bit must be programmed to specify the bus cycle in which DMARQ# will be negated as follows: NEGATE_COUNT = ...

Page 57

MultiBurst Mode Control Register Description: This 16-bit register controls the behavior of Mobile DiskOnChip P3 during MultiBurst mode read cycles. Address (hex): 101C Bit 7 Bit 6 Read/Write Description Reset Value 0 Bit 15 Bit 14 Read/Write Description Reset ...

Page 58

... ROM devices. When Mobile DiskOnChip P3 is located, the BIOS code executes from it the IPL code, located in the XIP portion of the Programmable Boot Block. This code loads the TrueFFS driver into system memory, installs Mobile DiskOnChip disk in the system, and then returns control to the BIOS code. The operating system subsequently identifies Mobile DiskOnChip available disk ...

Page 59

Mobile DiskOnChip P3 can be used as the only disk in the system, with or without a floppy drive, and with or without hard disks. The drive letter assigned depends on how Mobile DiskOnChip P3 is ...

Page 60

Non-PC Architectures In non-PC architectures, the boot code is executed from a boot ROM, and the drivers are usually loaded from the storage device. When using Mobile DiskOnChip P3 as the system boot device, the CPU fetches the first ...

Page 61

... C ESIGN ONSIDERATIONS 10.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 17. It may include the following devices: • Mobile DiskOnChip P3: Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It can also be used to perform boot operation, thereby replacing the need for a separate boot device. • ...

Page 62

... With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 18 below. Typically, Mobile DiskOnChip P3 can be mapped to any free 8KB memory space PC-compatible platform usually mapped into the BIOS expansion area. If the allocated memory window is larger than 8KB, an automatic anti-aliasing mechanism prevents the firmware from being loaded more than once during the ROM expansion search ...

Page 63

... Chip Enable (CE#) – Connect this signal to the memory address decoder. Most RISC processors include a programmable decoder to generate various Chip Select (CS) outputs for different memory zones. These CS signals can be programmed to support different wait states to accommodate Mobile DiskOnChip P3 timing specifications. • Power-On Reset In (RSTIN#) – Connect this signal to the host active-low Power-On Reset signal ...

Page 64

Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 18. Both signals must be connected to VSS if the host uses only one DiskOnChip. If more than one device is being used, refer to Section 10.6 for ...

Page 65

Implementing the Interrupt Mechanism 10.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball. ...

Page 66

Device Cascading When connecting Mobile DiskOnChip P3 256Mb using a standard interface four devices can be cascaded with no external decoding circuitry. Figure 20 illustrates the configuration required to cascade four devices on the host bus (only ...

Page 67

Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access Mobile DiskOnChip P3 during the boot sequence in order to load OS images and the device drivers. M-Systems’ ...

Page 68

Platform-Specific Issues Following is a description of hardware design issues for major embedded RISC processor families. 10.8.1 Wait State Wait states can be implemented only when Mobile DiskOnChip P3 is designed in a bus that supports a Wait state ...

Page 69

Data Access Mode When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even address accesses to the ...

Page 70

Design Environment Mobile DiskOnChip P3 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with Mobile DiskOnChip P3, even before the target platform is available. • Programming solutions: o GANG programmer ...

Page 71

P S RODUCT PECIFICATIONS 11.1 Environmental Specifications 11.1.1 Operating Temperature Commercial temperature range: Extended temperature range: -40°C to +85°C 11.1.2 Thermal Characteristics Junction to Case (θ 11.1.3 Humidity 10% to 90% relative, non-condensing 11.1.4 Endurance Mobile DiskOnChip P3 is ...

Page 72

Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Capacitance is not 100% tested. 11.2.3 DC Electrical Characteristics Over Operating Range See Table 10 and Table 11 for DC characteristics for VCCQ ranges 1.65-2.0V and 2.5-3.6V I/O, ...

Page 73

Symbol Parameter Maximum low-level output I OLmax current I Input leakage current ILK I Output leakage current IOLK V High-level output voltage OH V Low-level output voltage OL Active supply current VCC+VCCQ pins/balls Standby supply current, I CCS ...

Page 74

Timing Specifications 11.3.1 Read Cycle Timing Standard Interface t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 23: Standard Interface, Read Cycle Timing t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 24: Standard Interface ...

Page 75

Table 13: Standard Interface Read Cycle Timing Parameters Symbol Description Tsu(A) Address to OE# Tho(A) OE# to Address hold time Tsu(CE0) CE# to OE# setup time Tho(CE0) OE# to CE# hold time Tho(CE1) OE# or WE# to CE# Tsu(CE1) CE# ...

Page 76

Write Cycle Timing Standard Interface t SU A[12:0] t (CE1) HO CE# OE# WE# D[15:0] Figure 25: Standard Interface Write Cycle Timing Table 14: Standard Interface Write Cycle Parameters Symbol Description T (A) Address to WE# SU Tho(A) WE# ...

Page 77

Read Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 26: Multiplexed Interface Read Cycle Timing Table 15: Multiplexed Interface Read Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...

Page 78

Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 27: Multiplexed Interface Write Cycle Timing Table 16: Multiplexed Interface Write Cycle Parameters Symbol Description tsu(AVD) Address to AVD# tho(AVD) Address to ...

Page 79

Read Cycle Timing MultiBurst In Figure 28, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0. t (CLK1) W CLK t (OE0-CLK0) HO OE# t (OE0-CLK1 (OE0-CLK1) SU D[15:0] (HOLD=0) D[15:0] (HOLD=1) Insert LATENCY clock cycles Note: ...

Page 80

... Power-up Timing Mobile DiskOnChip P3 is reset by assertion of the RSTIN# input. When this signal is negated, Mobile DiskOnChip P3 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, Mobile DiskOnChip P3 does not respond to read or write accesses. ...

Page 81

VCC = 2.5V VCCQ = 1.65 or 2.5V VCC RSTIN# BUSY# A[12:0] CE#, OE# (WE (Read cycle) AVD# (Muxed Mode Only) DPD (A[0]) Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width ...

Page 82

Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 11.3.9 DMA Request Timing OE#/CE# DMARQ# Note: Polarity of DMARQ# may be inverted based on the NORMAL bit of DMA Control Register[0]. Symbol Tw(DMARQ#) DMARQ# asserted pulse width ...

Page 83

Mechanical Dimensions TSOP-I dimensions: 20.0±0. 12.0±0. 1.2±0.10 mm Figure 32: Mechanical Dimensions TSOP-I Package 80 Data Sheet, Rev. 0.3 Mobile DiskOnChip P3 93-SR-009-8L ...

Page 84

FBGA dimensions: 7.0±0. 10.0±0. 1.2±0.10 mm Ball pitch: 0.8 mm Figure 33: Mechanical Dimensions 7x10 FBGA Package 81 Data Sheet, Rev. 0.3 Mobile DiskOnChip P3 93-SR-009-8L ...

Page 85

... O I RDERING NFORMATION Device Code 5811 - DiskOnChip P3 TSOP-I 5832 - DiskOnChip P3 FBGA (7x10) Refer to Table 21 for combinations currently available and the associated order numbers. Ordering code MD5811-d256-V3Q18 MD5811-d256-V3Q18-X MD5811-d256-V3Q18-P MD5811-d256-V3Q18-X-P MD5832-d256-V3Q18-X MD5832-d256-V3Q18-X-P MD5832-d00-DAISY MD5811-d256-MECH MD5832-d256-MECH 82 MDxxxx-Dxxx-xxx-T-C Capacity D- MByte d- Mbit xxx - Value Supply Voltage V3Q18 - 3 ...

Page 86

ONTACT S USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA 94560 Phone: +1-510-494-2090 Fax: +1-510-494-5545 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: +81-3-5423-8102 ...

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