MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 68

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MD5811-D256-V3Q18-P

Manufacturer Part Number
MD5811-D256-V3Q18-P
Description
IC MDOC P3 256MB 48-TSOP
Manufacturer
SanDisk
Datasheet

Specifications of MD5811-D256-V3Q18-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
256M (32M x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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10.8 Platform-Specific Issues
Following is a description of hardware design issues for major embedded RISC processor families.
10.8.1 Wait State
Wait states can be implemented only when Mobile DiskOnChip P3 is designed in a bus that
supports a Wait state insertion, and supplies a WAIT signal.
10.8.2 Big and Little Endian Systems
Mobile DiskOnChip P3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least
Significant Byte (LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the
byte lanes, bit D0 and bit D8 are the least significant bits of their respective byte lanes. Mobile
DiskOnChip P3 can be connected to a Big Endian device in one of two ways:
1. Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data bus
2.
10.8.3 Busy Signal
The Busy signal (BUSY#) indicates that Mobile DiskOnChip P3 has not yet completed internal
initialization. After reset, BUSY# is asserted while the IPL is downloaded into the internal boot
block and the Data Protection Structures (DPS) are downloaded to the Protection State Machines.
Once the download process is completed, BUSY# is negated. It can be used to delay the first access
to Mobile DiskOnChip P3 until it is ready to accept valid cycles.
Note: The TrueFFS driver does NOT use this signal to indicate that the flash is in busy state (e.g.
10.8.4 Working with 8/16/32-Bit Systems
Mobile DiskOnChip P3 uses a 16-bit data bus and supports 16-bit data access by default. However,
it can be configured to support 8 or 32-bit data access mode. This section describes the connections
required for each mode.
The default of the TrueFFS driver for Mobile DiskOnChip P3 is set to work in 16-bit mode. It must
be specially configured to support 8 and 32-bit mode. Please see TrueFFS documentation for further
details.
Note: The DiskOnChip data bus must be connected to the Least Significant Bits (LSB) of the
65
so that the byte lanes of the CPU match the byte lanes of Mobile DiskOnChip P3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of Mobile DiskOnChip
P3, and prevents the TrueFFS driver from identifying it.
Set the bits SWAPH and SWAPL in the Endian Control register. This enables byte swapping
when used with 16-bit hosts.
program, read, or erase).
system. The system engineer must verify whether the matching host signals are SD[7:0],
SD[15:8] or D[31:24].
Data Sheet, Rev. 0.3
Mobile DiskOnChip P3
93-SR-009-8L

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